An introduction to time-triggered technology
Products from TTE Systems are based on time-triggered (TT) technology.
We explain what TT technology is, and the benefits of this approach, on this page.
For further information, you can download a whitepaper which provides an overview of the range of possible TT architectures and explains how use of this approach can help to reduce testing costs.
You may also be interested in some books on TT architectures (written by our team).
What is “time triggered technology”?
There are two main architectures used to develop software for modern embedded systems: these can be labelled as “event triggered” or “time triggered”.
For many developers, event-triggered (or “ET”) architectures are more familiar. ET designs involve creating systems which handle multiple interrupts. For example, interrupts may arise from periodic timer overflows, the arrival of messages on a CAN bus, the pressing of a switch, the completion of an analogue-to-digital conversion and so on. To create such systems, the developer may write code to handle the various events directly: this will typically involve creating an “interrupt service routine” to deal with each event. Alternatively, the developer may employ a conventional real-time operating system (RTOS) to support the event handling. Whether an RTOS is used or not, the end result is the same: the system must be designed in such a way that events – which may occur at “random” points in time, and in various combinations – can always be handled correctly.
The alternative to an event-triggered architecture is a time-triggered (“TT”) architecture. Although TT architectures are widely used in industries such as aerospace and medical systems, they are less familiar to developers of mainstream embedded systems. When implementing TT systems, the key thing we need to remember is the “one interrupt per CPU” rule. That is, TT designs only have one interrupt enabled. This single interrupt is usually linked to a timer “tick”, which might occur (for example) every millisecond. In a TT design, all other inputs are polled.
Learning to design with “just one interrupt” may sound like a significant challenge, but it’s much easier than you may imagine and use of a TT architecture can have very significant benefits for developers, not least a reduction in testing times.
What are the benefits of using TT architectures?
Use of TT architectures in your system can provide the following benefits:
- Reduced testing time (and lower maintenance costs)
- Reduced unit costs
- Ease of certification
We consider each of these issues in turn below.
Reduced testing time (and lower maintenance costs)
TT designs tend to have a very simple architecture: this makes them easy to understand, and easy to maintain.
System testing also tends to be more straightforward with TT designs and, because of the simplicity of the architecture, maintenance costs can be substantially reduced too.
If your company is still using a conventional RTOS, ask yourself how many of your team really understand how this works, in detail (be honest). If your team don’t fully understand the 1000s of lines of code in your RTOS, can you be sure exactly how your system will operate in the field?
For further information, you can download a whitepaper which explains how use of a TT approach can help to reduce testing costs.
Reduced unit costs
Many companies find that use of TT architectures helps to reduce costs of production, not least because it reduces system resource requirements.
This reduction in resource requirements arises in part because you don’t need a conventional RTOS to support a TT design.
Ease of certification
Many systems for use in aerospace, medical or automotive sectors require certification.
Because of the predictable nature of TT designs, certification authorities (and company lawyers) tend to look favourably upon the use of this architecture in safety-critical and safety-related systems.
Further reading
For further information, you can download a whitepaper which provides an overview of the range of possible TT architectures and explains how use of this approach can help to reduce testing costs.
You may also be interested in some books on TT architectures.