The TTE32® family of soft processor cores and related soft microcontrollers target a growing range of FPGA targets, including devices from Xilinx® and Altera®.


The TTE®32-TT3 is a 32-bit design with 32-registers and a five-stage pipeline. The processor is compatible with the MIPS-1 Instruction Set Architecture.
The TTE®32-TT3 Processor Core is intended to provide high levels of of performance and maximum levels of temporal predictability (in order to simplify design, test and maintenance activities). This is achieved in various ways. For example, the design employs a cachless (zero wait) Harvard architecture memory system with two separate ports to memory, one for instruction fetch and one for data access. In addition, hardware support for multiplication and division is provided: this is fully predictable, and is 33 clock cycles in current releases of the core.
Building on the TTE®32-TT3 core, the TTE®32-SM3 soft microcontroller can be used to implement a wide range of embedded systems, but this platform is particularly well suited to the creation of embedded systems with a time-triggered (TT) architecture.
The TTE®32-SM3 Microcontroller offers the following key benefits to the developers of embedded systems with a TT architecture:
The TTE®-SM3 microcontroller is a fully-supported target in RapidiTTy® MCU 2.3.


The TTE®-TT3 processor can be adapted and configured using RapidiTTy® FPGA 2.0.


Please contact us for further details.