5-day course: Design & verification of high-integrity embedded systems
Are you involved in the development of high-integrity embedded systems for use in aerospace, defence, medical, automotive or industrial sectors? Do you need to be able to guarantee that your systems will operate correctly? Do you need to “certify” your systems? If so, we may be able to help.
This popular 5-day training course begins by exploring key software (and hardware) architectures for high-integrity embedded systems and goes on to consider implementation, testing and verification issues. The full development lifecycle is considered.
Topics covered in the course include:
- Static analysis of executable code to determine worst-case execution time (WCET).
- Predicting, measuring and reporting maximum CPU loading values.
- The interaction between software architecture and hardware architecture (and why this should influence your choice of hardware platform).
- Maximising reliability through the use of dual-lane and “triplicated” hardware architectures. Use of protection systems (“intelligent” watchdogs). Maximising reliability while minimising costs.
- Techniques for testing reliable embedded systems from the code level (incl. statement coverage and “modified condition / decision coverage” - MCDC) to the system level (incl. the use of both processor simulators and hardware-in-the-loop testbeds).
- Techniques for scheduling complex task sets. Fixed-priority scheduling architectures (including rate-monotonic and deadline-monotonic algorithms, with or without task pre-emption). Automating schedulability analysis and scheduler configuration when using large task sets.
[Module code: A2a]
Course options
You can attend this course:
- As a self-contained 5-day training module.
- As part of the Certified Software Engineer (Reliable Embedded Systems) programme.
- As part of the University of Leicester’s MSc in Reliable Embedded Systems.
Course objectives
After attending this course, participants will understand:
- “Why, when and how” to use time-triggered software architectures
- How to choose an appropriate hardware platform
- How to design and implement tasks with deterministic behaviour
- How to carry out static analysis of executable task code to determine worst-case execution time (WCET) and best-case execution time (BCET)
- How to perform schedulability analysis and scheduler configuration for complex task sets
- How to predict and measure maximum CPU loading values
- How to test the resulting design, from the task level (incl. statement coverage and “modified condition / decision coverage” - MCDC) to the system level (incl. the use of both processor simulators and hardware-in-the-loop testbeds)
- How to link all of the above material together in order to meet standards and guidelines such as DO-178, IEC 61508, ISO 26262, EN 50128 and IEC 61513 without imposing high costs on the organisation concerned
Video introduction
You will find a short video introduction to this course on our YouTube® channel.
Who should attend?
This course will be of particular benefit to engineers and engineering managers interested in the development of high-integrity aviation, automotive, medical, defence, space, industrial, rail, telecomms, marine and civil nuclear systems.
Throughout the course, reference is made to “DO-178”, the civil-aviation benchmark against which approaches to the development of high-integrity systems (in all sectors) are judged at the present time. However, the course is not “aerospace specific” and examples from various sectors are discussed. For example, the course will help participants who wish to demonstrate compliance with standards and guidelines such as IEC 61508 (industrial), ISO 26262 (automotive), EN 50128 (railway systems) and IEC 61513 (civil nuclear systems).
Pre-requisites for this course
Most of coding examples (and some of the exercises) on this module involve the C programming language. We assume that all participants have had significant experience developing embedded systems using C.
Please note that this is not an introductory course. If you have worked with high-integrity embedded systems for less than 24 months, we strongly recommend that you:
- attend our course on “Programming techniques for reliable embedded systems” before taking this course, and / or;
- review the training materials for our Certified Embedded C programme.
When will this course be delivered next?
This course will next be delivered as follows:
- 20 to 24 February 2012 at the University of Leicester
- 30 July to 3 August 2012 at the University of Leicester
- 12 to 16 November 2012 at the University of Leicester
Early booking is recommended.
Places can be reserved by e-mail (places will be confirmed on receipt of payment).
We can also deliver this course on your site at any time: please contact us for details.
Price
Places are available on this course at the “Taster” rate of £500 + VAT per place.
Please note that you can take this course and “Programming techniques for reliable embedded systems” for the combined fee of £1200 + VAT (Taster rate).
Please refer to our fees page for full information.
Become a “Certified Software Engineer (Reliable Embedded Systems)”
Attending this course may help you to become a Certified Software Engineer (Reliable Embedded Systems).
Study by ‘Distance Learning’
You can prepare for the certification exam in your own time by “Distance Learning”: this involves reading the course notes, watching lectures on DVDs, completing exercises at home and interacting with a tutor by e-mail.
If you pass the exam at the appropriate level, you will receive a formal certificate [“Certified Software Engineer (Reliable Embedded Systems)”].
The fee for this option is £350 (VAT may be chargeable depending on your location).
You should allow around 16-20 weeks to prepare for certification by Distance Learning.
Join a public training course and then take the certification examination
You can attend the “live” 5-day training course in Leicester (as described on this WWW page) and then sit the certification exam.
If you pass the exam at the appropriate level, you will receive a formal certificate [“Certified Software Engineer (Reliable Embedded Systems)”].
The fee for this option (training and examination) is £950 + VAT.
In this case, both training and examination are usually held in Leicester: please contact us if you wish to take the exam in a different location.
You should allow around 8-12 weeks to prepare for certification if you start the process by attending a 5-day training course.
Booking instructions
To book a place on this course, please contact us.
A place will then be reserved and you will be sent an invoice.
Your place on the course will be confirmed when payment is received.
Formal quotations can be provided on request.
Methodology
This course is taught through a carefully-planned combination of seminars and practical (laboratory) classes. Problems are be set during seminars and in laboratory sessions.
Real-world case studies are used extensively in the seminars and laboratory sessions.
Trainer biodata
This module is delivered by Prof. Michael J. Pont from the University of Leicester, UK.
Michael Pont holds a BSc (Electrical and Electronic Engineering) from the University of Glasgow and a PhD (Computer Science) from the University of Southampton. Michael is Professor of Embedded Systems and Head of the Embedded Systems Research Group at the University of Leicester: he is also CEO of TTE Systems Ltd.
In 2010, Michael was the recipient of the “Best Presenter” award at the Embedded Masterclass.
Michael is author / co-author of more than 100 technical publications and author of three books (“[Patterns for Time-Triggered Embedded Systems]”, “Embedded C” and “Software Engineering with C++ and CASE Tools”).
Detailed course contents
Day 1: Static timing analysis and worst-case execution time
Introduction to the module. The central role of worst-case execution time (WCET) predictions in all real-time embedded systems. Links between WCET and CPU load. Links between WCET, software architecture, hardware architecture and CPU load. Obtaining WCET measurements quickly and efficiently. Why measuring WCET is rarely sufficient: the need for static analysis. Predicting WCET by means of static code analysis. Source code or executable code? The impact of compiler optimisation settings. Static analysis of simple code blocks. Dealing with conditional branches: making assumptions. Justifying and recording your assumptions. Hardware errors, software errors and WCET. Detecting errors and recovering from them. Introduction to exercises for Day 1.
Day 2: Time-triggered task scheduling
Key system architectures. Time-triggered vs. event-triggered architectures. Design for test. Time-triggered co-operative (TTC) and time-triggered hybrid (TTH) software architectures. Working with sets of periodic tasks. Key task parameters. Synchronous and asynchronous task sets: the impact of task offsets. Determining the length of the major cycle. Task deadlines and jitter. Schedulability analysis and scheduler configuration for TTC and TTH designs. The need to consider both normal operation and error handling. Introduction to exercises for Day 2.
Day 3: Fixed-priority task scheduling
Design of reliable embedded systems using fixed-priority schedulers. Rate-monotonic and deadline-monotonic scheduling algorithms. Periodic and sporadic tasks. Co-operative and pre-emptive solutions. Design challenges. Dealing with errors: should we switch to “earliest deadline first” (EDF)? Schedulabilty analysis and scheduler configuration. Tuning small systems by hand. Challenges with large task sets. Practical solutions. TTC / TTH vs. full FPS. RTOS issues. Certified RTOSs? Introduction to exercises for Day 3.
Day 4: How to spend less time testing your system
The need for reviews, analyses and testing. The links between requirements and testing. Testing challenges. Test scripts. Function stubs. Why we need to measure statement coverage. Measuring statement coverage. Why statement coverage isn’t enough. The need for “Modified Condition/Decision Coverage” (MC/DC). Performing MC/DC checks. Challenges with MC/DC. Testing your modules. Testing the system: HIL testbeds. Introduction to exercises for Day 4.
Day 5: Detailed case study
Introduction to the case study. Understanding the task set. Schedulability tests. Selecting suitable hardware: ISA. Selecting suitable hardware. Implementing the scheduler. Determining task WCET. Creating the test suite. Checking test coverage. Module conclusions.
Reliable, safety-related and safety-critical embedded systems
All of our training courses are designed to help participants who wish to improve the reliability of the embedded systems produced by their organisation. Beyond this general goal, some courses have a sharper focus on techniques which are appropriate for use in safety-related or safety-critical systems: a summary of these links is provided in the table below (please click on the table to increase the text size).
Embedded processors now have an enormous impact in many products, including - for example - high-end consumer applications such as washing machines and set-top boxes and various automotive applications (for example, control of door mirrors). Manufacturers need to maximise the reliability of such systems in order to reduce the cost of warranty repairs, minimise product recalls and ensure repeat orders. All of our courses are designed to support the developers of such reliable embedded systems.
In many cases, embedded processors are employed in safety-related systems: these include automotive, medical and industrial systems. In a safety-related design, the embedded processor will never have total control: there will always be some form of backup device — or “backup person” — available in the event that the embedded system operates incorrectly (or fails to operate at all). For example: [i] an automotive “anti-lock” braking system (ABS) may have a mechanical backup; [ii] a medical system may be used to provide information to a qualified clinician: the doctor will make the final treatment decision; [iii] a train control system may require final authorisation from the driver before moving the vehicle. Even with the availability of a “backup” option, great reliance is placed on safety-related embedded systems and they must — clearly — be developed with great care.
The challenges facing the developer become even more significant when we start to consider safety-critical embedded systems. In such systems the system cannot rely on external backups option, and failure is likely to result in injury or death, either to users of the system (for example, with a medical design) or those in the vicinity (for example, with an aerospace or industrial design). Without doubt, the development of safety-critical embedded systems represents one of the greatest challenges faced by engineers on the planet today.
It should also be noted that — while failure of a particular embedded system may not result in loss of life — it may still be appropriate to develop the systems to “safety critical” standards. Such an approach may be considered (for example) when developing business-related applications where failure would result in huge financial losses (for example, some forms of electronic trading system for use in a stock exchange, or a system used to monitor electricity usage in consumer homes).
Course options
This course is delivered by TTE Systems Ltd.
You can attend this course as a self-contained 5-day training module or as part of the University of Leicester’s MSc in Reliable Embedded Systems.
Interested in on-site training?
We can deliver this course on your site at any time.
For on-site courses:
- Training duration can be anything from 1 to 10 days.
- Course content can be adapted to meet your precise requirements.
- Training can be delivered anywhere in the world.
- Combinations of training and consultancy activities can be provided.
Please contact us for further details.
On-site training options are only cost effective for class sizes of at least 10 people in most cases.
Related publications
Since the 1990s, members of our team have been involved in the development of a range of techniques and tools which support the creation and verification of time-triggered embedded systems. Over this period, we have contributed to a number of publications in this field, many of which are in the public domain. A list of some relevant publications is included below.
Embedded C
“Embedded C” provides an introduction to the programming of embedded systems using time-triggered software architectures.
- Pont, M.J.(2002) “Embedded C”, Addison-Wesley. ISBN: 0-201-79523-X.
- Pont, M.J.(2003) “Embedded C”, Chinese Electric Power Press. ISBN: 7-5083-1814-5.
- Pont, M.J.(2004) “Embedded C”, Pearson Education Taiwan. ISBN: 986-7491-52-1.
- Pont, M.J.(2008) “Embedded C”, Dorling Kindersley (India) Pvt. Ltd. ISBN: 978-81-317-1589-5.
Patterns for time-triggered embedded systems
“Patterns for Time-Triggered Embedded Systems” provides more detailed coverage of the use of time-triggered techniques in reliable embedded systems.
Please note that “PTTES” can now be downloaded without charge from this website.
- Pont, M.J.(2001) “Patterns for Time-Triggered Embedded Systems”, Addison-Wesley / ACM Press. ISBN: 0-201-331381.
- Pont, M.J.(2004) “Patterns for time-triggered embedded systems”, Chinese Electric Power Press ISBN: 7-5083-2206-1.
Other relevant publications
Ahmad, N. and Pont, M.J.(2009) “Remote debugging of embedded systems which employ a time-triggered architecture”, Proceedings of the 5th UK Embedded Forum, Leicester, UK, 23-24 September, 2009, pp.97-106. Published by Newcastle University. ISBN 978-0-7017-0222-9.
Ahmad, N. and Pont, M.J.(2010) “Debugging remote embedded systems: The impact of system software architecture”, Proceedings of the 2010 UK Electronics Forum, Newcastle, UK, 30 June-1 July, 2010, pp.17-23. Published by Newcastle University. ISBN 978-0-7017-0232-8.
Amir, M. and Pont, M.J.(2008) “Synchronising tasks in wireless multi-processor environments using a shared-clock architecture: A pilot study”, Proceedings of the 4th UK Embedded Forum, Southampton, UK, 9-10 September, 2008, pp.30-39. Published by IET. ISBN 978-0-8634-1949-2.
Amir, M. and Pont, M.J.(2009) “A time-triggered communication protocol for CAN-based networks with a star topology”, Proceedings of the 5th UK Embedded Forum, Leicester, UK, 23-24 September, 2009, pp.30-44. Published by Newcastle University. ISBN 978-0-7017-0222-9.
Amir, M. and Pont, M.J.(2010) “A novel shared-clock scheduling protocol for fault-confinement in CAN-based distributed systems”, Proceedings of the 5th IEEE International Conference on System of Systems, IEEE SoSE 2010, Loughborough University, UK, 22nd-24th, June 2010.
Amir, M. and Pont, M.J.(2010) “A time-triggered communication protocol for CAN-based networks with a fault-tolerant star topology “, Proceedings of the International Symposium on Advanced Topics in Embedded Systems and Applications under the 7th IEEE International Conference on Embedded Software and Systems, Bradford, West Yorkshire, UK, 29th June-1st July, 2010. ISBN 978-0-7695-4108-2.
Amir, M. and Pont, M.J.(2010) “Integration of TTC-SC5 and TTC-SC6 shared-clock protocols”, Proceedings of the 1st UK Electronics Forum, Newcastle, UK, 30th June-1st July, 2010. Published by Newcastle University. ISBN 978-0-7017-0232-8.
Athaide, K., Hughes, Z.M. and Pont, M.J.(2007) “Towards a time-triggered processor”, Proceedings of the 3rd UK Embedded Forum, Durham, UK, 203 April, 2007, pp.166. Published by IET. ISBN 9780863418037. ISSN 0537-9989.
Athaide, K.F., Pont, M.J. and Ayavoo, D. (2008) “Deploying a time-triggered shared-clock architecture in a multiprocessor system-on-chip design”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).
Athaide, K.F., Pont, M.J. and Ayavoo, D. (2008) “Shared-clock methodology for time-triggered multi-cores”, in Susan Stepney, Fiona Polack, Alistair McEwan, Peter Welch, and Wilson Ifill (Eds.), “Communicating Process Architectures 2008”, IOS Press.
Ayavoo, D., Pont, M.J. and Parker, S. (2004) “Using simulation to support the design of distributed embedded control systems: A case study”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.54-65. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].
Ayavoo, D., Pont, M.J. and Parker, S. (2005) “Observing the development of a reliable embedded system”. In Vardanega, T and Wellings, A. (Eds.) “Proceedings of the 10th Ada-Europe International Conference on Reliable Software Technologies, York, UK, June 20-24 2005”, pp. 167-179. Lecture Notes in Computer Science, Vol. 3555. Published by Springer-Verlag [ISBN: 3-540-26286-5]
Ayavoo, D., Pont, M.J. and Parker, S. (2006) “Does a ‘simulation first’ approach reduce the effort involved in the development of distributed embedded control systems?”. Proceedings of the 6th UKACC International Control Conference, Glasgow, Scotland, 2006.
Ayavoo, D., Pont, M.J., Fang, J., Short, M. and Parker, S. (2005) “A ‘Hardware-in-the Loop’ testbed representing the operation of a cruise-control system in a passenger car”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.60-90. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Ayavoo, D., Pont, M.J., Short, M. and Parker, S. (2005) “Two novel shared-clock scheduling algorithms for use with CAN-based distributed systems”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.246-261. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Ayavoo, D., Pont, M.J., Short, M. and Parker, S. (2007) “Two novel shared-clock scheduling algorithms for use with CAN-based distributed systems”, Microprocessors and Microsystems, 31(5): 326-334.
Bautista, R., Pont, M.J. and Edwards, T. (2005) “Comparing the performance and resource requirements of ‘PID’ and ‘LQR’ algorithms when used in a practical embedded control system: A pilot study”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.262-289. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Bautista-Quintero, R. and Pont, M.J.(2006) “Is fuzzy logic a practical choice in resource-constrained embedded control systems implemented using general-purpose microcontrollers?”, Proceedings of the 9th IEEE International Workshop on Advanced Motion Control (Istanbul, March 27-29, 2006), Volume 2, pp.692-697. IEEE catalog number 06TH8850. ISBN 0-7803-9511-5.
Bautista-Quintero, R. and Pont, M.J.(2008) “Implementation of H-infinity control algorithms for sensor-constrained mechatronic systems using low-cost microcontrollers”, IEEE Transactions on Industrial Informatics, 16(4): 175-184.
Chan, K.L. and Pont, M.J.(2010) “Real-time non-invasive detection of timing-constraint violations in time-triggered embedded systems”, Proceedings of the 7th IEEE International Conference on Embedded Software and Systems, Bradford, UK, 2010, pp.1978-1986. Published by IEEE Computer Society. ISBN 978-0-7695-4108-2.
Edwards, T., Pont, M.J., Scotson, P. and Crumpler, S. (2004) “A test-bed for evaluating and comparing designs for embedded control systems”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.106-126. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].
Edwards, T., Pont, M.J., Short, M.J., Scotson, P. and Crumpler, S. (2005) “An initial comparison of synchronous and asynchronous network architectures for use in embedded control systems with duplicate processor nodes”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.290-303. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Gendy, A. and Pont, M.J.(2007) “Towards a generic ‘single-path programming’ solution with reduced power consumption”, Proceedings of the ASME 2007 International Design Engineering Technical Conferences & Computers and Information in Engineering Conference (IDETC/CIE 2007), September 4-7, 2007, Las Vegas, Nevada, USA.
Gendy, A. and Pont, M.J.(2008) “Automating the processes of selecting an appropriate scheduling algorithm and configuring the scheduler implementation for time-triggered embedded systems”, Proceedings of The 27th International Conference on Computer Safety, Reliability and Security (SAFECOMP08), 22-25 September 2008, Newcastle upon Tyne, UK
Gendy, A. and Pont, M.J.(2008) “Automating the processes of selecting an appropriate scheduling algorithm and configuring the scheduler implementation for time-triggered embedded systems”, Proceedings of The 27th International Conference on Computer Safety, Reliability and Security (SAFECOMP08), 22-25 September 2008, Newcastle upon Tyne, UK
Gendy, A., Dong, L. and Pont, M.J.(2007) “Improving the performance of time-triggered embedded systems by means of a scheduler agent”, Proceedings of the ASME 2007 International Design Engineering Technical Conferences & Computers and Information in Engineering Conference (IDETC/CIE 2007), September 4-7, 2007, Las Vegas, Nevada, USA.
Gendy, A.K. and Pont, M.J.(2008) “Automatically configuring time-triggered schedulers for use with resource-constrained, single-processor embedded systems”, IEEE Transactions on Industrial Informatics, 4(1): 37-46.
Hanif, M., Pont, M.J. and Ayavoo, D. (2008) “Implementing a simple but flexible time-triggered architecture for practical deeply-embedded applications”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).
Hughes, Z.H. and Pont, M.J.(2004) “Design and test of a task guardian for use in TTCS embedded systems”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.16-25. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].
Hughes, Z.M. and Pont, M.J.(2008) “Reducing the impact of task overruns in resource-constrained embedded systems in which a time-triggered software architecture is employed”, Transactions of the Institute of Measurement and Control, Vol. 30: pp.427-450.
Hughes, Z.M., Pont, M.J. and Ong, H.L.R.(2005) “Design and evaluation of a “time-triggered” microcontroller”. Poster presentation at DATE 2005 (PhD Forum), Munich, Germany, March 2005.
Hughes, Z.M., Pont, M.J. and Ong, H.L.R.(2005) “The PH Processor: A soft embedded core for use in university research and teaching”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.224-245. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Imran, S., Short, M. and Pont, M.J.(2008) “Hardware implementation of a shared-clock scheduling protocol for CAN: A pilot study”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).
Imran, S., Short, M. and Pont, M.J.(2008) “Hardware implementation of a shared-clock scheduling protocol for CAN: A pilot study”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).
Key, S. and Pont, M.J.(2004) “Implementing PID control systems using resource-limited embedded processors”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.76-92. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].
Key, S.A., Pont, M.J. and Edwards, S. (2004) “Implementing low-cost TTCS systems using assembly language”. In: Henney, K. and Schutz, D. (Eds) Proceedings of the Eighth European conference on Pattern Languages of Programs (EuroPLoP 8), Germany, June 2003: pp.667-690. Published by Universitätsverlag Konstanz. ISBN 3-87940-788-6.
Koelmans, A., Bystrov, A. and Pont, M.J.(2004)(Eds.) “Proceedings of the First UK Embedded Forum” (Birmingham, UK, October 2004). Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].
Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (2005)(Eds.) “Proceedings of the Second UK Embedded Forum” (Birmingham, UK, October 2005). Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Kurian, S. and Pont, M.J.(2005) “Building reliable embedded systems using Abstract Patterns, Patterns, and Pattern Implementation Examples”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.36-59. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Kurian, S. and Pont, M.J.(2005) “Mining for pattern implementation examples”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.194-201. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Kurian, S. and Pont, M.J.(2006) “Evaluating and improving pattern-based software designs for resource-constrained embedded systems”. In: C. Guedes Soares & E. Zio (Eds), “Safety and Reliability for Managing Risk: Proceedings of the 15th European Safety and Reliabilty Conference (ESREL 2006), Estoril, Portugal, 18-22 September 2006”, Vol. 2, pp.1417-1423. Published by Taylor and Francis, London. ISBN: 0-415-41620-5 (for complete 3-volume set of proceedings). ISBN: 978-0-415-42314-4 (for Volume 2).
Kurian, S. and Pont, M.J.(2007) “Maintenance and evolution of resource-constrained embedded systems created using design patterns”, Journal of Systems and Software, 80(1): 32-41.
Lakhani, F. and Pont, M.J.(2010) “Using design patterns to support migration between different system architectures”, Proceedings of 5th IEEE International Conference on Systems of Systems Engineering, June 2010, Loughborough , UK.
Lakhani, F., and Pont, M.J.(2010) “Code balancing as a philosophy for change: Helping developers to migrate from event-triggered to time-triggered architectures” Proceedings of First UK Electronics Forum, 30June- 1 July 2010, Newcastle, UK , Published by Newcastle University. ISBN: 978-0-7017-0232-8
Lakhani, F., Pont, M.J. and Das, A. (2009) “Can we support the migration from event triggered to time triggered architectures using design patterns?” Proceedings of 5th UK Embedded Forum, Leicester, UK , pp. 62-67. Published by Newcastle University. ISBN: 978-0-7017-0222-9
Lakhani, F., Pont, M.J. and Das, A. (2009) “Towards a pattern language which supports the migration of systems from an event-triggered pre-emptive to a time-triggered co-operative software architecture” Proceedings of 14th Annual European Conference on Pattern Languages of Programming”, Irsee, Germany, 8-12 July 2009. published by CEUR vol. 566 . ISSN : 1613-0073
Lakhani, F., Pont, M.J. and Das, A. (2010) “Creating embedded systems with predictable patterns of behaviour, supporting the migration between event-triggered and time-triggered software architectures” Proceedings of 15th Annual European Conference on Pattern Languages of Programming” , Irsee, Germany, 7 -11 July 2010.
Li, Y. and Pont, M.J.(2002) “On selecting pre-processing techniques for fault classification using neural networks: A pilot study”, International Journal of Knowledge-Based Intelligent Engineering Systems, 6(2): 80-87.
Li, Y., Pont, M.J. and Jones, N.B.(2002) “Improving the performance of radial basis function classifiers in condition monitoring and fault diagnosis applications where ‘unknown’ faults may occur”, Pattern Recognition Letters, 23: 569-577.
Li, Y., Pont, M.J., and Jones, N.B.(1999) “A comparison of the performance of radial basis function and multi-layer Perceptron networks in a practical condition monitoring application”, Proceedings of Condition Monitoring 1999 [Swansea, UK, April 12-15, 1999] pp.577-592.
Li, Y., Pont, M.J., Jones, N.B. and Twiddle, J.A.(2001) “Using MLP and RBF classifiers in embedded condition monitoring and fault diagnosis applications”, Transactions of the Institute of Measurement & Control, 23(3): 313-339.
Li, Y., Pont, M.J., Parikh, C.R. and Jones, N.B.(2000) “Comparing the performance of three neural classifiers for use in embedded applications”, in: John, R. and Birkenhead, R. (Eds.) Advances in Soft Computing: Soft Computing Techniques and Applications, Springer-Verlag, Heidelberg, pp.34-39, [ISBN 3-7908-1257-9]
Li, Y.H., Jones, N.B. and Pont, M.J.(1998) “Applying neural networks and fuzzy logic to fault diagnosis: a review”. in John, R.I.(1998), Editor, “Proceedings of: ‘Recent Advances in Soft Computing ‘98” [Leicester, July 1998] pp.104-119. Published by DeMontfort Expertise, Leicester, UK [ISBN 185 721 2592].
Maaita, A. and Pont, M.J.(2005) “Using ‘planned pre-emption’ to reduce levels of task jitter in a time-triggered hybrid scheduler”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.18-35. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Mearns, D.D.U., Pont, M.J. and Ayavoo, D. (2008) “Towards Ctt (a programming language for time-triggered embedded systems)”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).
Muhammad, A. and Pont, M.J.(2008) “Synchronising tasks in wireless multi-processor environments using a shared-clock architecture: A pilot study”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).
Muhammad, A. and Pont, M.J.(2011) “Comments on: Two novel shared-clock scheduling algorithms for use with CAN-based distributed systems”, Microprocessors and Microsystems, Vol. 35, pp.81-82.
Mwelwa, C. and Pont, M.J.(2003) “Two new patterns to support the development of reliable embedded systems” Paper presented at the Second Nordic Conference on Pattern Languages of Programs, (“VikingPLoP 2003”), Bergen, Norway, September 2003.
Mwelwa, C., Athaide, K., Mearns, D., Pont, M.J. and Ward, D. (2007) “Rapid software development for reliable embedded systems using a pattern-based code generation tool”. SAE Transactions: Journal of Passenger Cars (Electronic and Electrical Systems), 115(7): 795-803.
Mwelwa, C., Pont, M.J. and Ward, D. (2004) “Code generation supported by a pattern-based design methodology”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.36-55. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].
Mwelwa, C., Pont, M.J. and Ward, D. (2004) “Using patterns to support the development and maintenance of software for reliable embedded systems: A case study”, Proceedings of the IEE / ACM Postgraduate Seminar on “System-On-Chip Design, Test and Technology”, Loughborough, UK, 15 September 2004. Published by IEE. ISBN: 0 86341 460 5 (ISSN: 0537-9989), pp. 15-20.
Mwelwa, C., Pont, M.J. and Ward, D. (2005) “Developing reliable embedded systems using a pattern-based code generation tool: A case study”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.177-193. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Nahas, M. and Pont, M.J.(2005) “Using XOR operations to reduce variations in the transmission time of CAN messages: A pilot study”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.4-17. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Nahas, M., Pont, M.J. and Jain, A. (2004) “Reducing task jitter in shared-clock embedded systems using CAN”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.184-194. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].
Nahas, M., Pont, M.J. and Short, M.J.(2009) “Reducing message-length variations in resource-constrained embedded systems implemented using the Controller Area Network (CAN) protocol”, Journal of Systems Architecture Vol. 55: pp.344–354.
Nahas, M., Short, M.J. and Pont, M.J.(2005) “Exploring the impact of software bit stuffing on the behaviour of a distributed embedded control system implemented using CAN”, in Proceedings of the 10th international CAN Conference, held in Rome, 8-10 March 2005, pp. 10-1 to 10-7.
Ong, H.L.R and Pont, M.J.(2001) “Empirical comparison of software-based error detection and correction techniques for embedded systems”, Proceedings of the 9th International Symposium on Hardware / Software Codesign, April 25-27 2001, Copenhagen, Denmark. Pp.230-235. Published by ACM Press, New York. ISBN: 1-58113-364-2.
Ong, H.L.R and Pont, M.J.(2002) “The impact of instruction pointer corruption on program flow: a computational modelling study”, Microprocessors and Microsystems, 25: 409-419
Ong, H.L.R, Pont, M.J. and Peasgood, W. (2001) “A comparison of software-based techniques intended to increase the reliability of embedded applications in the presence of EMI” Microprocessors and Microsystems, 24(10): 481-491.
Ong, H.L.R., Pont, M.J., and Peasgood, W. (2000) “Hardware-software tradeoffs when designing microcontroller-based applications for high-EMI environments”, IEE Colloquium on Hardware-Software Co-Design, Savoy Place, London, 8 December, 2000. IEE Colloquium Digests #111.
Parikh C.R., M.J. Pont and N.B. Jones (2001) “Application of Dempster-Shafer theory in condition monitoring systems”, Pattern Recognition Letters, 22(6-7): 777-785.
Parikh C.R., Pont, M.J., Jones, N.B. and Schlindwein, F.S.(2003) “Improving the performance of CMFD applications using multiple classifiers and a fusion framework”, Transactions of the Institute of Measurement and Control, 25(2): 123-144.
Parikh, C., Pont, M.J., Jones, N.B., Bhatti, A.I., Li, Y.H., Spurgeon, S.K., Scotson, P. and Scaife, M. (1998) “Towards an application framework for condition monitoring and fault diagnosis”. In John, R.I.(1998), Editor, “Proceedings of: ‘Recent Advances in Soft Computing ‘98” [Leicester, July 1998] pp.128-141. Published by DeMontfort Expertise, Leicester, UK [ISBN 185 721 2592].
Parikh, C.R., Pont, M.J., Li, Y. and Jones, N.B.(1999) “Improving the performance of multi-layer Perceptrons where limited training data are available for some classes”, Proceedings IEE International Conference on Neural Networks, Edinburgh, September 1999, pp.227-232.
Parikh, C.R., Pont, M.J., Li, Y. and Jones, N.B.(1999) “Neural networks for condition monitoring and fault diagnosis: The effect of training data on classifier performance”, Proceedings of Condition Monitoring 1999 [Swansea, UK, April 1999] pp.237-244.
Parikh, C.R., Pont, M.J., Li, Y. and Jones, N.B.(2000) “Investigating the performance of MLP classifiers where limited training data are available for some classes”, in: John, R. and Birkenhead, R. (Eds.) Advances in Soft Computing: Soft Computing Techniques and Applications, Springer-Verlag, Heidelberg, pp.22-27, [ISBN 3-7908-1257-9]
Parikh, C.R., Pont, M.J., Li, Y.H., Jones, N.B. and Twiddle, J.A.(1998) “Towards a flexible application framework for data fusion using real-time design patterns,” Proceedings of 6th European Congress on Intelligent Techniques & Soft Computing (EUFIT), Aachen, Germany, September 7-10, 1998. pp.1131-1135.
Phatrapornnant, T. and Pont, M.J.(2004) “The application of dynamic voltage scaling in embedded systems employing a TTCS software architecture: A case study”, Proceedings of the IEE / ACM Postgraduate Seminar on “System-On-Chip Design, Test and Technology”, Loughborough, UK, 15 September 2004. Published by IEE. ISBN: 0 86341 460 5 (ISSN: 0537-9989), pp. 3-8.
Phatrapornnant, T. and Pont, M.J.(2004) “The application of dynamic voltage scaling in embedded systems employing a TTCS software architecture”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.127-143. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].
Phatrapornnant, T. and Pont, M.J.(2006) “Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling”, IEEE Transactions on Computers, 55(2): 113-124.
Pont, M.J.(1996) “Software Engineering with C++ and CASE Tools”, Addison-Wesley [964 pages]. ISBN: 0-201-87718-X.
Pont, M.J.(1998) “Control system design using real-time design patterns”, Proceedings of Control ‘98 (Swansea, UK), September 1998, pp.1078-1083.
Pont, M.J.(2000) “Can patterns increase the reliability of embedded hardware-software co-designs?”, IEE Colloquium on Hardware-Software Co-Design, Savoy Place, London, 8 December, 2000. IEE Colloquium Digests #111.
Pont, M.J.(2000) “Designing and implementing reliable embedded systems using patterns”, in, Dyson, P. and Devos, Martine (Eds.) “EuroPLoP ‘99: Proceedings of the 4th European Conference on Pattern Languages of Programming and Computing, 1999”. ISBN 3-87940-774-6, Universitätsverlag Konstanz.
Pont, M.J.(2001) “Patterns for Time-Triggered Embedded Systems: Building Reliable Applications with the 8051 Family of Microcontrollers”, Addison-Wesley / ACM Press. [1012 pages] ISBN: 0-201-331381.
Pont, M.J.(2002) “Embedded C”, Addison-Wesley. [302 pages] ISBN: 0-201-79523-X.
Pont, M.J.(2003) “An object-oriented approach to software development for embedded systems implemented using C”, Transactions of the Institute of Measurement and Control 25(3): 217-238.
Pont, M.J.(2003) “Supporting the development of time-triggered co-operatively scheduled (TTCS) embedded software using design patterns”, Informatica, 27: 81-88.
Pont, M.J.(2008) “Applying time-triggered architectures in reliable embedded systems: Challenges and solutions”, Elektrotechnik & Informationstechnik, Vol. 125(11): 401-405.
Pont, M.J. and Banner, M.P.(2004) “Designing embedded systems using patterns: A case study”, Journal of Systems and Software, 71(3): 201-213.
Pont, M.J. and Mwelwa, C. (2003) “Developing reliable embedded systems using 8051 and ARM processors: Towards a new pattern language” Paper presented at the Second Nordic Conference on Pattern Languages of Programs, (“VikingPLoP 2003”), Bergen, Norway, September 2003.
Pont, M.J. and Ong, H.L.R.(2003) “Using watchdog timers to improve the reliability of TTCS embedded systems”, in Hruby, P. and Soressen, K. E.[Eds.] Proceedings of the First Nordic Conference on Pattern Languages of Programs, September, 2002 (“VikingPloP 2002”), pp.159-200. Published by Micrsoft Business Solutions. ISBN: 87-7849-769-8.
Pont, M.J., Kureemun, R., Ong, H.L.R. and Peasgood, W. (1999) “Increasing the reliability of embedded automotive applications in the presence of EMI: A pilot study”, IEE Colloquium on Automotive EMC, Birmingham, September 28, 1999.
Pont, M.J., Kurian, S. and Bautista-Quintero, R. (2007) “Meeting real-time constraints using ‘Sandwich Delays’”. In: Zdun, U. and Hvatum, L. (Eds) Proceedings of the Eleventh European conference on Pattern Languages of Programs (EuroPLoP ‘06), Germany, July 2006: pp.67-77. Published by Universitätsverlag Konstanz. ISBN 978-3-87940-813-9.
Pont, M.J., Kurian, S., Wang, H. and Phatrapornnant, T. (2007) “Selecting an appropriate scheduler for use with time-triggered embedded systems” Paper presented at the 12th European Conference on Pattern Languages of Programs (EuroPLoP 2007).
Pont, M.J., Li, Y., Parikh, C.R. and Wong, C.P.(1999) “The design of embedded systems using software patterns”, Proceedings of Condition Monitoring 1999 [Swansea, UK, April 12-15, 1999] pp.221-236.
Pont, M.J., Norman, A.J., Mwelwa, C. and Edwards, T. (2004) “Prototyping time-triggered embedded systems using PC hardware”. In: Henney, K. and Schutz, D. (Eds) Proceedings of the Eighth European conference on Pattern Languages of Programs (EuroPLoP 8), Germany, June 2003: pp.691-716. Published by Universitätsverlag Konstanz. ISBN 3-87940-788-6.
Rizvi, S.A.I. and Pont, M.J.(2009) “Hardware support for deadlock-free resource sharing in an embedded system with a TT architecture”, Proceedings of 5th UK Embedded Forum 2009, University of Leicester, UK, 23-24 September, pp. 1-9. Published by Newcastle University. ISBN: 978-0-7017-0222-9
Short, M. and Pont, M.J.(2005) “Hardware in the loop simulation of embedded automotive control systems”, in Proceedings of the 8th IEEE International Conference on Intelligent Transportation Systems (IEEE ITSC 2005) held in Vienna, Austria, 13-16 September 2005, pp. 226-231.
Short, M. and Pont, M.J.(2006) “Predicting the impact of hardware redundancy on the performance of embedded control systems”. Proceedings of the 6th UKACC International Control Conference, Glasgow, Scotland, 30 August to 1 September, 2006.
Short, M. and Pont, M.J.(2007) “Fault-tolerant time-triggered communication using CAN”, IEEE Transactions on Industrial Informatics, 3(2): 131-142.
Short, M. and Pont, M.J.(2008) “Assessment of high-integrity embedded automotive control systems using Hardware-in-the-Loop simulation”, Journal of Systems and Software, 81(7): 1163-1183.
Short, M., Fang, J., Pont, M.J. and Rajabzadeh, A. (2007) “Assessing the impact of redundancy on the performance of a brake-by-wire system”. SAE Transactions: Journal of Passenger Cars (Electronic and Electrical Systems), 115(7): 331-338.
Short, M., Pont, M.J. and Fang, J. (2008) “Assessment of performance and dependability in embedded control systems: Methodology and case study”, Control Engineering Practice. Vol. 16, pp.1293– 1307
Short, M., Pont, M.J. and Fang, J. (2008) “Exploring the impact of task pre-emption on dependability in time-triggered embedded systems: A pilot study”, Proceedings of the 20th EUROMICRO Conference on Real-Time Systems (ECRTS 08), Prague, Czech Republic, July 2nd - 4th, 2008
Short, M., Pont, M.J. and Fang, J. (2008) “Exploring the impact of task pre-emption on dependability in time-triggered embedded systems: A pilot study”, Proceedings of the 20th EUROMICRO Conference on Real-Time Systems (ECRTS 08), Prague, Czech Republic, July 2nd - 4th, 2008
Vidler, P.J. and Pont, M.J.(2005) “Automatic conversion from ‘single processor’ to ‘multi-processor’ software architectures for embedded control systems”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.209-223. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].
Vidler, P.J. and Pont, M.J.(2006) “Computer assisted source-code parallelisation”. In: Gavrilova, M., Gervasi, O., Kumar, V., Tan, C.J.K., Taniar, D., Laganà, A., Mun, Y. and Choo, H. (eds.) Proceedings of the IEE International Conference on Computational Science and its Applications (Glasgow, May 8-11, 2006), Part V. Lecture Notes in Computer Science (LNCS), Vol. 3984, pp.22-31.
Vladimirova, T, Bannister, N.P., Fothergill, J.C., Fraser, G..W, Lester, M., Wright, D., Pont, M.J., Barnhart, D.J. and Emam, O. (2011) “CubeSat mission for space weather monitoring”, Proceedings of the 11th Australian Space Science Conference, September 26-29 2011.
Wang, H. and Pont, M.J.(2008) “Design and implementation of a static pre-emptive scheduler with highly predictable behaviour”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).
Wang, H. and Pont, M.J.(2008) “Design and implementation of a static pre-emptive scheduler with highly predictable behaviour”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).
Wang, H., Pont, M.J. and Kurian, S. (2007) “Patterns which help to avoid conflicts over shared resources in time-triggered embedded systems which employ a pre-emptive scheduler” Paper presented at the 12th European Conference on Pattern Languages of Programs (EuroPLoP 2007).