Home › 5-day …

5-day course: Soft. & Sys. Arch. with a focus on DO-178b / ED-12b (Ada)

Are you involved in the development of high-integrity embedded systems for use in aerospace, defence, medical, automotive or industrial sectors? Do you need to be able to guarantee that your systems will operate correctly? Do you need to “certify” your systems?

This 5-day course begins by exploring key software architectures for high-integrity embedded systems and goes on to consider both implementation and testing issues. The course also considers the impact that the choice of hardware platform may have on the ability to predict system behaviour.

Many of the examples discussed in the course - including the main case study on Day 5 - address issues (including determination of CPU loading, WCET prediction and MC/DC testing) which are of concern in projects developed according to RTCA DO-178b / EUROCAE ED-12b and related guidelines.

This course is delivered by TTE Systems Ltd.

University of Leicester This course can be taken as a 5-day short course or as part of the University of Leicester’s MSc in Reliable Embedded Systems.

[Module code: A2b]

Learn how to develop high-integrity embedded systems (with a focus on DO-178b)

Topics covered in the course include:

  • Static analysis of executable code to determine worst-case execution time (WCET).
  • Predicting, measuring and reporting maximum CPU loading values.
  • The interaction between software architecture and hardware architecture.
  • Fixed-priority scheduling architectures (including rate-monitonic and deadline-monitonic algorithms, with or without task pre-emption). Automating schedulability analysis and scheduler configuration when using large task sets.
  • Techniques for testing reliable embedded systems from the code level (incl. statement coverage and “modified condition / decision coverage” - MCDC) to the system level (incl. the use of both processor simulators and hardware-in-the-loop testbeds).

Who should attend?

This course will be of particular benefit to engineers and engineering managers interested in the development of high-integrity aerospace, defence, medical, automotive and industrial systems.

Programming language

Most code examples on this course will be based on the ‘Ada’ programming language.

We also offer a ‘C’-language version of this course.

When will this course be delivered next?

Please contact us for information about delivery dates.

Registration details

To register for this course, please contact us.

A place will then be reserved and you will be sent an invoice.

Your place on the course will be confirmed when payment is received.

Formal quotations can be provided on request.

Price

Places are available on this course at the “Taster” rate of £500 + VAT per place.

Please note that you can take this course and Module A1 for the combined fee of £1200 + VAT (Taster rate).

Please refer to our fees page for full information.

Pre-requisites for this course

If you have not previously worked with embedded systems, we recommend that you attend Module A1 before taking this module.

Most of coding examples and exercises on this module involve the Ada programming language.

Some (limited) programming experience with Ada is assumed. You may like to know that some example Ada programs are included with RapidiTTy Lite.

Trainer biodata

This module will be delivered by Prof. Michael J. Pont from the University of Leicester, UK.

Michael Pont holds a BSc (Electrical and Electronic Engineering) from the University of Glasgow and a PhD (Computer Science) from the University of Southampton. Michael is Professor of Embedded Systems and Head of the Embedded Systems Laboratory at the University of Leicester: he is also CEO of TTE Systems Ltd.

In 2010, Michael was the recipient of the “Best Presenter” award at the Embedded Masterclass.

Michael is author / co-author of more than 100 technical publications and author of three books (“Patterns for Time-Triggered Embedded Systems”, “Embedded C” and “Software Engineering with C++ and CASE Tools”).

Detailed course contents

Day 1: Static timing analysis and worst-case execution time

Introduction to the module. The central role of worst-case execution time (WCET) predictions in all real-time embedded systems. Links between WCET and CPU load. Links between WCET, software architecture, hardware architecture and CPU load. Obtaining WCET measurements quickly and efficiently. Why measuring WCET is rarely sufficient: the need for static analysis. Predicting WCET by means of static code analysis. Source code or executable code? The impact of compiler optimisation settings. Static analysis of simple code blocks. Dealing with conditional branches: making assumptions. Justifying and recording your assumptions. Hardware errors, software errors and WCET. Detecting errors and recovering from them. Introduction to exercises for Day 1.

Day 2: Time-triggered task scheduling

Key system architectures. Time-triggered vs. event-triggered architectures. Design for test. Time-triggered co-operative (TTC) and time-triggered hybrid (TTH) software architectures. Working with sets of periodic tasks. Key task parameters. Synchronous and asynchronous task sets: the impact of task offsets. Determining the length of the major cycle. Task deadlines and jitter. Schedulability analysis and scheduler configuration for TTC and TTH designs. The need to consider both normal operation and error handling. Introduction to exercises for Day 2.

Day 3: Fixed-priority task scheduling

Design of reliable embedded systems using fixed-priority schedulers. Rate-monotonic and deadline-monotonic scheduling algorithms. Periodic and sporadic tasks. Co-operative and pre-emptive solutions. Design challenges. Dealing with errors: should we switch to “earliest deadline first” (EDF)? Schedulabilty analysis and scheduler configuration. Tuning small systems by hand. Challenges with large task sets. Practical solutions. TTC / TTH vs. full FPS. RTOS issues. Certified RTOSs? Introduction to exercises for Day 3.

Day 4: How to spend less time testing your system

The need for reviews, analyses and testing. The links between requirements and testing. Testing challenges. Test scripts. Function stubs. Why we need to measure statement coverage. Measuring statement coverage. Why statement coverage isn’t enough. The need for “Modified Condition/Decision Coverage” (MC/DC). Performing MC/DC checks. Challenges with MC/DC. Testing your modules. Testing the system: HIL testbeds. Introduction to exercises for Day 4.

A380

Day 5: Detailed aerospace case study

Introduction to the case study. Understanding the task set. Schedulability tests. Selecting suitable hardware: ISA. Selecting suitable hardware. Implementing the scheduler. Determining task WCET. Creating the test suite. Checking test coverage. Module conclusions.

Methodology

This course is taught through a carefully-planned combination of seminars and practical (laboratory) classes. Problems will be set during seminars and in laboratory sessions. Case studies will be used extensively in the laboratory sessions.

Links to the MSc programme in Reliable Embedded Systems

University of Leicester This course can be taken as a 5-day short course or as part of the University of Leicester’s MSc in Reliable Embedded Systems.

You may also be interested in …

Downloads (free of charge)

A full list of available training modules

Related products

At TTE Systems, we help our customers to create reliable embedded systems.

We develop and sell high-integrity processors, both ‘off the shelf’ & custom software development tools and advanced safety protection mechanisms (‘shutdown systems’). We also offer a range of training, consultancy and custom design services.

Application sectors for our products and services range from aerospace, medical, industrial, automotive, defence and satellite systems to high-end consumer goods.

Many of our products can be provided in forms which are suitable for use in DO-178b, DO-254, ED-80, IEC 61508 (SIL3) , ISO 26262 (ASIL D) and similar high-integrity and safety-critical projects.