MSc in Reliable Embedded Systems - Modules
There are six modules on the MSc in Reliable Embedded Systems. Details are provided on this page.
Please note that:
- The same modules are delivered in the UK and in Malaysia, but the delivery dates, are different.
- You can begin the MSc programme with any module
- The modules can also be taken as individual short courses. Please note that the short courses are open to anyone (there are no educational requirements and no need for references, etc). To take these modules, you can simply register to attend one of the public courses. Please contact us for pricing and registration details.
- The individual modules can also be delivered as stand-alone short courses anywhere in the world. When delivering short courses in this way, we are happy to adapt the course length and course content to match your precise requirements. Please contact us for further information about on-site short courses.
- The field of embedded systems changes rapidly, and our modules are updated frequently. The module details provided here illustrate the typical range of topics which are considered in each module, and the depth of coverage. The detailed module contents are subject to change without notice.
Programming techniques for reliable embedded systems
[University of Leicester module ID: EG7510 - A1]
Overview
This module considers programming techniques for reliable embedded systems.
The module is taught mainly using the “C” programming language, with coverage of “MISRA C”.
This module provides an ideal “entry point” for the MSc programme.
Module contents
Day 1: An introduction to “Embedded C”
On Day 1, the world of embedded systems is introduced using a series of short seminars interleaved with practical sessions which are designed to reinforce the key concepts. C is the standard programming language for embedded systems: working with a processor simulator and an 8-bit target, you will learn how to create your first programs in “Embedded C”. Starting by flashing an LED, you will soon move on to learn how to create reliable code for working with switches and taking control of the real world.
Day 2: Real-time “Embedded C”
On Day 2, we move on to look at the need for simple operating systems, and the concepts of “real time” constraints. We consider and discuss concepts such as worst-case execution time, task jitter and time-out mechanisms. By the end of the day, you’ll have created and tested a complete set of code for your first realistic embedded systems.
Day 3: Exploring modern hardware platforms
In the first two days of this course, we focus on software development and you’ll work with a simple processor simulator to test your code. On Day 3, we move into the 21st century: you’ll by start creating code for a modern (32-bit) microcontroller with an ARM® processor core. After you’ve got your first system running, you’ll learn about debugging (including the use of JTAG) and timing analysis.
Modern embedded systems use a wide range of platforms. To round off Day 3, we’ll look at two further targets.
- In recent years, the Intel® Atom processor has become the basis of many “embedded PCs”. We’ll consider some of the challenges involved in creating reliable systems based on this type of platform. As you’ll learn, your embedded PC will run happily without a “conventional” operating system (we won’t be using Windows® or Linux: instead we’ll be programming “at the bare metal” for maximum predictability and performance).
- We’ll then go on to look at “Field programmable gate arrays” (FPGAs). FPGAs are already a popular implementation platform for developers of embedded systems (and some people believe that they will be the platform of choice for the majority of new systems within the next few years). We’ll introduce you to some of the challenges and opportunities offered by this exciting new platform. As you’ll see, FPGAs provide enormous flexibility, allowing you to create a custom processor target for every project.
Day 4: Dealing with multiple tasks
In Day 4, we begin to look at some more advanced topics, including issues associated with task design (including task pre-emption). We’ll explore rate-monotonic (RM) and earliest deadline first (EDF) scheduling for single-processor systems. We’ll end Day 4 by taking a first look at techniques for working with distributed systems (using multiple processors connected by means of a Controller Area Network - or CAN - bus).
Day 5: Programming guidelines, MISRA C and design patterns
On Day 5, we’ll begin by discussing the use of the MISRA C programming guidelines and the ways in which the use of this “safe subset” of the C language can assist in the creation of reliable systems (there’s a lot to take in: you’ll be provided with your own printed copy of these guidelines to review at your leisure). We’ll then introduce the topic of “design patterns” and begin to see how this approach can be used to help organisations capture and re-use good design experience.
Target architecture
This module is taught using microcontrollers, FPGAs and an “embedded PC” as the target.
Related laboratory software
Laboratory exercises employ RapidiTTy tools.
If you take this module as a short course, you will receive a permanent (non-commercial) licence for the latest version of RapidiTTy MCU as part of your course fee.
If you take this module as part of the MSc programme, you will receive a permanent (non-commercial) licence for RapidiTTy Pro as part of your course fee.
What do I need to know before I start this module?
During this module, we assume that you know how to program (ideally in C, but – if you are prepared to do some homework before the module – a background in C++ or Java will also be appropriate).
Some experience with embedded systems is also assumed.
We don’t assume that you have had previous experience with the programming of reliable embedded systems.
Dates
Information about delivery dates …
Using FPGAs in reliable embedded systems
[University of Leicester module ID: EG7540 - B1]
Overview
Developers of modern embedded systems have two main implementation options:
- Employ a “commercial off-the-shelf” (COTS) processor.
- Implement their design using a “field-programmable gate array” (FPGA) and a “soft” processor core.
As the cost of FPGAs continues to fall, the opportunity to implement embedded systems using soft processor cores is becoming of increasing interest. This module addresses the key challenges involved in using FPGA technology in reliable embedded systems.
Module contents
Seminar 1 – Introduction to the world of hardware definition languages
Basics of HDL and digital logic; Concurrent statements (AND, OR gates etc); Sequential statements (Flip-flops); Understanding FPGA technology; Introduction to HDL tools (synthesis, fit & route).
Seminar 2 – Introduction to VHDL
Why use VHDL? Packages, Components and architecture; Top level modules; Libraries (IEEE); Port map; Signals / variables; Process & sensitivity lists; FPGA vs. ASIC; Modelsim & test benches
Seminar 3 – Understanding a processor instruction set Why use the MIPS instruction set? Addition and Subtraction; Immediates; Data Transfers; Decision Instructions; Inequalities; Arithmetic Overflow; Logic Instructions; Function call conventions; Stack Memory; Register Conventions; Instruction Formats; R-Format Instructions; I-Format Instructions; Branches: PC-Relative Addressing; J-Format Instructions
Seminar 4 – From instruction set to computer architecture
Computer Components; The datapath; Datapath examples; CPU clocking; ALU requirements; Hardware building blocks; Memory; Register file; Supporting branch operations; Datapath to control signals; Controller implementation; Performance through pipelining; Problems for pipelining CPUs
Seminar 5 – Advanced computer architecture
ILP; Superscalar pipelines; VLIW; Out-of-Order pipelines; Branch prediction; Precise Interrupt mechanisms; History buffer; Re-order buffer; Future file
Seminar 6 – Memory Systems
The memory hierarchy; Memory caching; Cache design; Direct-mapped cache; Problems with direct-mapped cache; Cache hits; Cache misses; Fully associative cache; N-Way set associative cache; Block replacement policy; Improving miss penalty; DMA; MMU; TLB
Seminar 7 – Problems of predictability
While real-time embedded systems require predictable timing behaviour at a hardware level; Obtaining safe and accurate timing measurements; Design principles for a time-predictable processor; Issues with current processor architectures (Instruction set; Pipelines; Branch prediction; Memory systems; Documentation); Long timing effects; Timing anomalies.
Seminar 8 – Making processor behaviour more predictable
How to ensure that interrupt response times are predictable. The “one interrupt per microcontroller” rule. Exploring options for hardware scheduling.
Seminar 9 – Basic techniques for error prevention and error recovery
What can possibly go wrong? Why deal with errors at the hardware level? Comparison of timing behaviour for software- and hardware-based recovery mechanisms.
Seminar 10 – Case study: a highly-predictable processor
Review of course material. A complete design for a predictable processor. Programming the predictable processor. Comparison of timing behaviour for “standard” and predictable processor.
Exercises
In parallel with the seminars, the course involves a carefully-planned sequence of exercises. Using state-of-the art development tools and carefully-selected target hardware, you will create your own predictable processor over the course of the week. Starting with some introductory sessions in VHDL, you will then begin to create your processor (starting with the program counter, instruction memory and register file). By the end of the week, you will have created a complete processor (with watchdog timer), which you will ultimately be able to program in C.
No previous experience with VHDL or processor design is assumed prior to the start of the course.
Module variations
Want to work Verilog (rather than VHDL) in this module? Please contact us for details.
Target architecture
This module is taught using an FPGA as the target.
If you are registered for the MSc programme, you will receive a package containing a target board, debugger, cables and other related equipment on loan for the duration of the module (free of charge). If you wish, you can purchase the equipment at the end of the module.
Related laboratory software
Laboratory exercises employ RapidiTTy FPGA.
If you take this module as a short course, you will receive a permanent (non-commercial) licence for the latest version of RapidiTTy FPGA as part of your course fee.
If you take this module as part of the MSc programme, you will receive a permanent (non-commercial) licence for RapidiTTy Pro as part of your course fee.
What do I need to know before I start this module?
During this module, we assume that you know how to program (ideally in C, but – if you are prepared to do some homework before the module – a background in C++ or Java will also be appropriate).
Some experience with embedded systems is also assumed.
We don’t assume that you have had previous experience with FPGAs or with VHDL.
Please note that teaching material on VHDL (and some self-study exercises) will be distributed in advance of this module. We ask that you review this material before you begin the module.
Module dates
Information about delivery dates …
Using an RTOS in a reliable embedded system
[University of Leicester module ID: EG7550 - B2]
Overview
Does your company use a real-time operating system (RTOS)? Does every member of your development team fully understand how this RTOS works? If not, can you be sure that your products will operate reliably?
We believe that the best way to fully understand the operation and effective use of an RTOS is to build one from scratch. This module therefore involves designing and building a complete RTOS (with support for time-triggered tasks, event handling and task-pre-emption).
The focus throughout the module is on understanding the ways in which RTOS features (and configuration settings) may have an impact on system behaviour. The module considers issues such as conflicts over shared resources and explores practical solutions using “priority inheritance”, “timed resource access” and related protocols.
Lessons learned from the module can be applied when using a wide range of commercial RTOS products.
The module also considers the related issue of safety standards and the certification of reliable embedded systems. Coverage includes DO-178, IEC 61508 and IEC 61131.
Module contents
- Seminar 1. Introduction. This seminar provides an overview of the course, reviews key material and introduces important related concepts. Includes: Why does a desktop system have an OS? Does a desktop system need an OS? Different ways of meeting timing constraints in RT designs.
- Seminar 2. Einstein’s approach to the RTOS. The simple TTC schedule. From schedule to RTOS. Challenges with one-to-many mappings from scheduling algorithm to RTOS implementation. Discussion of work by Nahas.
- Seminar 3. Adding support for task pre-emption using a TTH schedule. From schedule to OS. Possible locking mechanisms and their implementation. Is TTH static or dynamic? The TRAP protocol (Maaita) and related designs. Keeping the goal posts fixed: maintaining a single task set for use with both TTC and TTH designs.
- Seminar 4. User tasks (Part 1). What does an ideal user task look like? It can be argued that in an ideal world, WCET = BCET (Discuss). Code balancing in theory. Code balancing in practice. We can’t ignore the hardware. Dealing with changes to the task set and the task characteristics.
- Seminar 5. From rate-monotonic (RM) schedule to RTOS (Part 1). From TTH to TTRM: what a difference an additional priority level makes. Reviewing critical sections, locks and priority inversion in a multi-priority system. Example: Even NASA gets it wrong (the Mars Pathfinder). Implementing efficient locking mechanisms. Minimising change: maintaining the same task set. Checking the design: Analysis tools and run-time trials.
- Seminar 6. From rate-monotonic (RM) schedule to RTOS (Part 2). Minimising change: maintaining the same task set. Checking the design: Analysis tools and run-time trials.
- Seminar 7. From earliest-deadline first (EDF) schedule to RTOS (Part 1). Co-operative designs revisited: EDFCos. Full support for dynamic tasks. Can we still maintain the task set? What about custom (user) tasks?
- Seminar 8. From earliest-deadline first (EDF) schedule to RTOS (Part 2). Events, dear boy, events. Full support for events. Can we still maintain the task set? What about custom (user) tasks? Maximising temporal predictability in a complex world. Is it safe to fly in this?
- Seminar 9. User tasks (Part 2). The RTOS may change but the task set must be maintained. Avoiding the need to adapt task sets to match RTOS characteristics. Code balancing revisited. Determining WCET: techniques and tools.
- Seminar 10. Review session. Presentation and discussion of a representative case study. Review of the work conducted in the module and consideration of alternative approaches and solutions. Suggestions for further reading. To include a comparison different RTOS implementation strategies and feature sets and a consideration of the implications of safety standards and the certification of reliable embedded systems (e.g. DO-178, IEC 61508 and IEC 61131).
Target architecture
This module is taught using an ARM7 microcontroller as the target.
If you are registered for the MSc programme, you will receive a package containing a target board, JTAG debugger, cables and other related equipment on loan for the duration of the module (free of charge). If you wish, you can purchase the equipment at the end of the module.
Related laboratory software
Laboratory exercises employ RapidiTTy MCU.
If you take this module as a short course, you will receive a full permanent licence for the latest version of RapidiTTy MCU as part of your course fee.
If you take this module as part of the MSc programme, you will receive a full permanent licence for RapidiTTy Pro as part of your course fee.
What do I need to know before I start this module?
During this module, we assume that you know how to program (ideally in C, but – if you are prepared to do some homework before the module – a background in C++ or Java will also be appropriate).
Some experience with embedded systems is also assumed.
We don’t assume that you have had previous experience with real-time operating systems.
Module dates
Information about delivery dates …
Multi-processor and multi-core designs for reliable embedded systems
[University of Leicester module ID: EG7560 - B3]
Overview
This module considers the challenges involved in creating distributed (multi-processor) designs and the related challenges involved with multi-core (“Network on Chip”) designs.
The module covers key issues such as: Assigning tasks to processors / cores; Clock synchronisation and GALS designs; Suitable communication protocols (incl. RS-232, RS-485, CAN, Flexray); Ensuring reliable data transfers; Using multiple processor cores to enhance fault tolerance.
The module also discusses IEC 61499.
Module contents
- Seminar 1. Introduction. This module considers the challenges involved in creating distributed (multi-processor) designs and the related challenges involved with multi-core (“Network on Chip”) designs This seminar begins by providing an overview of the module, reviews key background material and introduces important related concepts.
- Seminar 2. The Controller Area Network (CAN) protocol. Creating a simple multi-processor design using CAN. The challenges of clock synchronisation. Timing of tasks and network communications. Basic use of watchdogs. Babbling idiot failures and how to handle them. Running without clock synchronisation.
- Seminar 3. Improving reliability in distributed designs. Adding redundant Master nodes. Adding redundant Slave nodes. Hot standbys. What can possibly go wrong? Adding redundant communication paths. Bus vs. star topologies. How do we compare performance of different architectures? Safety Integrity Levels.
- Seminar 4. Working with multi-core COTS processor (Part 1). Improving performance. Multi-processor vs. multi-core: similarities and differences. Maintaining design integrity when migrating from a single-processor solution.
- Seminar 5. Working with multi-core COTS processor (Part 2). Improving reliability. Implementing safety agents. Migrating long tasks. Creating an “event processor”. Avoiding resource conflicts in multi-core designs.
- Seminar 6. Creating a multi-core design on an FPGA (Part 1). Advantages of custom designs. Disadvantages. Clock synchronisation and GALS designs. Do we need formal methods?
- Seminar 7. Creating a multi-core design on an FPGA (Part 2). A closer look at “event processors”. A closer look at long tasks.
- Seminar 8. Design challenges. Scheduling issues. Maintenance. Adapting task sets for distributed systems. Example automotive control system.
- Seminar 9. A closer look at timing issues. Impact of jitter. Different forms of clock synchronisation algorithm. What happens when something goes wrong. Timing in the event of errors.
- Seminar 10. Review session. Presentation and discussion of a representative case study. Review of the work conducted in the module and consideration of alternative approaches and solutions. Suggestions for further reading. To include discussions about: standard communication protocols; relevant standards; IEC 61499.
Target architecture
This module is taught using both microcontrollers and FPGAs as the targets.
If you are registered for the MSc programme, you will receive a package containing target boards, debugger hardware, cables and other related equipment on loan for the duration of the module (free of charge). If you wish, you can purchase the equipment at the end of the module.
Related laboratory software
Laboratory exercises employ RapidiTTy MCU and RapidiTTy FPGA.
If you take this module as a short course, you will receive full permanent licences for the latest version of both RapidiTTy MCU and RapidiTTy FPGA as part of your course fee.
If you take this module as part of the MSc programme, you will receive a full permanent licence for RapidiTTy Pro as part of your course fee.
What do I need to know before I start this module?
During this module, we assume that you know how to program (ideally in C, but – if you are prepared to do some homework before the module – a background in C++ or Java will also be appropriate).
Some experience with embedded systems is also assumed.
We don’t assume that you have had previous experience with distributed or multi-core systems.
Please note that teaching material on VHDL (and some self-study exercises) will be distributed in advance of this module. We ask that you review this material before you begin the module.
Module dates
Information about delivery dates …
Software and system architectures for reliable embedded systems
[University of Leicester module ID: EG7520 - A2]
Overview
This module discusses the choice of software architecture for use in reliable embedded systems. The module aims to challenge established assumptions and explore the implications of different design decisions.
The module covers: Event-triggered designs; Time-triggered designs; Comparisons (predictability, power consumption, etc); Hybrid ET /TT designs; Case studies (e.g. scheduler and system designs for predictable and low power systems).
Both theoretical and practical exercises are used to compare the impact of different design decisions on system behaviour.
Module contents
- Seminar 1: Foundations. This seminar provides an overview of the course, reviews key material and introduces some important related concepts. Includes: Course overview; Review: Real-time systems and terminology; Review: Fundamentals of computational complexity and its implications for real-time embedded systems.
- Seminar 2: Software and System Architecture. This seminar describes the basic software and system architectures that designers have available to implement a given specification. Includes: The scheduler: the heart of the system architecture; The taxonomy of scheduling; Static vs. dynamic scheduling; Event- vs. time-triggering; Periodic, sporadic and hybrid task sets; Preemption and non-preemption; Synchronous systems; Offset-free and asynchronous systems; Implicit and constrained deadline systems; Important theoretical results.
- Seminar 3: Practical scheduler implementations (1): Engineering and analysis of a time-triggered, co-operative (TTC) scheduler. This seminar describes – in depth – the practical aspects of engineering a TTC scheduler, gives a full code implementation of such a scheduler, and describes how appropriate analysis may be performed to ensure the resulting system design is both predictable and reliable.
- Seminar 4: Practical scheduler implementations (2): Engineering and analysis of a non-preemptive Earliest-Deadline-First scheduler. This seminar describes – in depth – the practical aspects of engineering npEDF schedulers, gives a full code implementation of such a scheduler, and describes how appropriate analysis may be performed to ensure the resulting system design is both predictable and reliable.
- Seminar 5: Context Switch. This seminar looks in-depth into the context switch mechanism, and examines the advantages (and disadvantages) this brings in practical schedulers. Includes: Predictability vs determinism; Flexibility vs dependability; Allowing limited preemption: the hybrid TTC scheduler; Allowing full preemption: implementing the context switch; Implications of concurrency; Resource sharing and locking mechanisms; Run-time overheads; Case study.
- Seminar 6: Practical scheduler implementations (3): Engineering and analysis of a fixed-priority preemptive scheduler. This seminar describes – in depth – the practical aspects of engineering fixed-priority preemptive schedulers, gives a full code implementation of such a scheduler, and describes how appropriate analysis may be performed to ensure the resulting system design is both predictable and reliable.
- Seminar 7: Practical scheduler implementations (4): Engineering and analysis of a fully-preemptive Earliest-Deadline-First scheduler. This seminar describes – in depth – the practical aspects of engineering dynamic-priority preemptive schedulers, gives a full code implementation of such a scheduler, and describes how appropriate analysis may be performed to ensure the resulting system design is both predictable and reliable.
- Seminar 8: Hybrid Systems. This seminar covers alternate approaches to system and scheduler design, and introduces suitable approaches for analysis of the resulting system designs. Includes: Common features of the commercial RTOS; Analysing systems with release jitter; Layering priority-driven interrupts over a scheduler core; Allowing limited preemption; On-chip schedulers; Off chip (co-processor) schedulers.
- Seminar 9: Dynamic Voltage Scaling (DVS). This seminar introduces the concept of DVS, and shows how it may be used to reduce power consumption in an embedded design. Includes: What is DVS; Why DVS is a good match for time-triggered, non-preemptive systems; Using DVS in TTC schedulers; Using DVS in npEDF schedulers.
- Seminar 10: Case Study: the implications of system architecture on dependability. The final seminar describes a representative case study, which illustrates the possible impact that the choice of underlying system and software architecture may have on the dependability of the resulting system.
Target architecture
This module is taught using an ARM7 microcontroller as the target.
If you are registered for the MSc programme, you will receive a package containing a target board, JTAG debugger, cables and other related equipment on loan for the duration of the module (free of charge). If you wish, you can purchase the equipment at the end of the module.
Related laboratory software
Laboratory exercises employ RapidiTTy MCU.
If you take this module as a short course, you will receive a full permanent licence for the latest version of RapidiTTy MCU as part of your course fee.
If you take this module as part of the MSc programme, you will receive a full permanent licence for RapidiTTy Pro as part of your course fee.
What do I need to know before I start this module?
During this module, we assume that you know how to program (ideally in C, but – if you are prepared to do some homework before the module – a background in C++ or Java will also be appropriate).
Some experience with embedded systems is also assumed.
We don’t assume that you have had previous experience with software / system architectures for reliable embedded systems.
Module dates
Information about delivery dates …
Design patterns for reliable embedded systems
[University of Leicester module ID: EG7530 - A3]
Overview
The aim of this module is to explore ways in which a company can capture the expertise of its best designers and make this available to other development teams within their organisation.
The approach discussed in this module is based on the use of “design patterns”.
The module covers: What are patterns? Patterns for reliable embedded systems; How are patterns developed? Understanding (and running) pattern workshops; Capturing design expertise (creating your own patterns); Workshops on company patterns.
Module contents
- Seminar 1. Introduction and motivation This seminar introduces the course. To illustrate how design patterns can be used to support the rapid development of reliable embedded systems, the origins and evolution of the “PTTES” collection is discussed. Key concepts are introduced.
- Seminar 2. The work of Christopher Alexander This seminar focuses on the landmark work of Christopher Alexander who introduced the concept of patterns. Examples of Alexander’s patterns are presented and discussed.
- Seminar 3. Patterns everywhere Seminar 3 introduces the concept of software design patterns that has evolved from Alexander’s original ideas. The influential work of the ‘Gang of Four’ (GoF) is discussed. Various pattern ‘forms’ (GoF, POSA, etc.) are presented and the main elements of a pattern (problem, solution, context, forces, etc) are examined. Some examples of patterns that have been successfully applied to various other fields such as teaching and organisational management are also presented.
- Seminar 4. Patterns for fault-tolerant software Seminar 4 considers patterns which have been developed to support the design and implementation of fault-tolerant systems. The focus is on the Hanmer pattern collection.
- Seminar 5. Second-generation pattern languages for embedded systems Seminar 5 considers the challenges of creating software patterns for embedded systems which (a) contain useful low-level details, and (b) can be adapted for use with different hardware targets. The seminar discusses how second-generation pattern languages have been developed which address these issues, and discusses practical techniques for creating such languages.
- Seminar 6. Identifying and documenting good patterns. In Seminar 6, John Vlissides’ seven habits of successful pattern writers are discussed. The seminar also explores the process of “mining” for patterns in an organisation.
- Seminar 7. Refining your patterns: The “Shepherding” process. Seminar 7 considers how patterns are ‘shepherded’, in preparation for a pattern workshop. The seminar considers the skills required to act as a good shepherd and the shepherding process. A pattern language for shepherding is also presented
- Seminar 8. Refining your patterns: Running a “Writers’ Workshop”.
Seminar 8 demonstrates how to run a pattern workshop. Tips for holding a successful pattern workshop will be presented. A pattern language for writers’ workshops is also discussed. - Seminar 9. Assessing the effectiveness of your pattern language. There have been many “silver bullets” in the software world, techniques which have “guaranteed” that your future projects will always be completed on time and on budget. Instead of making rash claims, Seminar 9 explores cost-effective and practical ways in which you can obtain real data to determine whether your pattern language will be effective in your organisation.
- Seminar 10. The future of “pattern-based software engineering” for embedded systems.
Seminar 10 considers what Kurian has called “pattern-based software engineering” (PBSE). Tool support for PBSE is considered. In addition, possible applications of patterns in support of the maintenance of embedded systems is considered. We wrap up the course by reviewing the strengths and weaknesses of pattern-based design approaches for the developers of reliable embedded systems.
Target architecture
This module is taught using both microcontrollers and FPGAs as the targets.
If you are registered for the MSc programme, you will receive a package containing target boards, JTAG debugger, cables and other related equipment on loan for the duration of the module (free of charge). If you wish, you can purchase this equipment at the end of the module.
Related laboratory software
Laboratory exercises employ RapidiTTy MCU.
If you take this module as a short course, you will receive a full permanent licence for the latest version of RapidiTTy MCU as part of your course fee.
If you take this module as part of the MSc programme, you will receive a full permanent licence for RapidiTTy Pro as part of your course fee.
What do I need to know before I start this module?
During this module, we assume that you know how to program (ideally in C, but – if you are prepared to do some homework before the module – a background in C++ or Java will also be appropriate).
Some experience with embedded systems is also assumed.
We don’t assume that you have had previous experience with design patterns.
Module dates
Information about delivery dates …