- High-integrity processors – Software tools – Protection systems – Training - Custom designs - Consultancy -

This practical 5-day training course explores key techniques for working with multiple CPUs in high-integrity embedded systems. The system configurations considered during this course are as follows:

• “Lock step” designs involving two (or more) CPUs in a single processor unit. In such a design, each CPU executes the same program code. Any differences between the activities on the two CPUs may indicate an error (caused, for example, by electromagnetic interference of a single-event effect).
• Multi-core designs involving two (or more) CPUs is a single processor unit. In such a design, the different cores will usually perform different activities. Such designs can - if implemented correctly - improve performance and may reduce power consumption (when compared with a single-core equivalent design). However care must be taken to ensure that communication between cores and / or access to shared resources (such as shared memory) do not give rise to reliability problems.
• Multi-processor (distributed) designs involving multiple processor units connected using CAN, Ethernet, RS-485 or similar protocols. In such designs the slow data transfers (compared with a multi-core design), the need to synchronise activities on the different cores and the possibility of processor and / or communication bus failures must all be taken into account when creating a reliable system.

[Module code: B3a]

Course options

You can attend this course:

• As a self-contained 5-day training module.
• As part of the Certified Senior Developer (Reliable Embedded Systems) programme.
• As part of the University of Leicester’s MSc in Reliable Embedded Systems.

Who should attend?

This course will be of particular benefit to engineers and engineering managers interested in the development of high-integrity aerospace, defence, medical, automotive and industrial systems.

Pre-requisites for this course

Most of coding examples (and some of the exercises) on this module involve the C programming language. We assume that all participants have had experience developing embedded systems using C.

Please note that this is not an introductory course. If have worked with embedded systems for less than 6-12 months, we recommend that you attend Module A1 before taking this course.

When will this course be delivered next?

This course will next be delivered as follows:

• 11 to 14 June 2012 at the University of Leicester

Price

Places are available on this course at the “Taster” rate of £500 + VAT per place.

Please note that you can attend this course and Module A1a for the combined fee of £1200 + VAT (Taster rate).

Conditions apply to all “Taster rate bookings. Please refer to our fees page for full information.

Booking instructions

To book a place on this course, please contact us.

A place will then be reserved and you will be sent an invoice.

Your place on the course will be confirmed when payment is received.

Formal quotations can be provided on request.

Course contents

Day 1: Working with ‘lock step’ and related processor architectures

Introduction. Safety Integrity Levels (SILs) and related concepts. Meeting SIL requirements. Potential reliability issues with single-processor designs. Possible distributed designs. Creating a “lock step”. Working with lock-step hardware: programming issues and challenges. Consideration of COTS and custom lock-step solutions. Alternative ways of meeting SIL requirements. Case studies from different sectors. ISO 26262, IEC 61508, DO-254 and DO-178 considerations.

Day 2: Making effective use of multi-core processors in reliable systems (Part 1)

Improving performance with multiple cores. Multi-processor vs. multi-core: similarities and differences. Maintaining design integrity when migrating from a single-processor solution. Scheduling issues. Maintenance. Adapting task sets for distributed systems. Example automotive control system.

Day 3: Making effective use of multi-core processors in reliable systems (Part 2)

Improving reliability. Implementing safety agents. Migrating long tasks. Creating an “event processor”. Avoiding resource conflicts in multi-core designs. Advantages of custom designs. Disadvantages. Clock synchronisation and GALS designs. Do we need formal methods? Impact of jitter. Different forms of clock synchronisation algorithm. What happens when something goes wrong? Timing in the event of errors. Case study.

Day 4: Creating reliable distributed systems

Creating a simple multi-processor design using CAN. The challenges of clock synchronisation. Timing of tasks and network communications. Basic use of watchdogs. Babbling idiot failures and how to handle them. Running without clock synchronisation. Adding redundant Master nodes. Adding redundant Slave nodes. Hot standbys. What can possibly go wrong? Adding redundant communication paths. Bus vs. star topologies. How do we compare performance of different architectures? Safety Integrity Levels. The impact of high bandwidths on software designs.

Day 5: Detailed case study

Presentation and discussion of a representative case study. Review of the work conducted in the module and consideration of alternative approaches and solutions. Suggestions for further reading.

Course options

This course is delivered by TTE Systems Ltd.

You can attend this course as a self-contained 5-day training module or as part of the University of Leicester’s MSc in Reliable Embedded Systems.

Interested in on-site training?

We can deliver this course on your site at any time.

For on-site courses:

• Training duration can be anything from 1 to 10 days.
• Course content can be adapted to meet your precise requirements.
• Training can be delivered anywhere in the world.
• Combinations of training and consultancy activities can be provided.

Please contact us for further details.

On-site training options are only cost effective for class sizes of at least 10 people in most cases.