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An introduction to time-triggered technology

Products and services from TTE Systems are based on time-triggered architectures.

Time-triggered (TT) architectures have been used for many years in industries such as aerospace and defence, because they have been found to provide significant benefits (including high system reliability and greatly reduced testing costs). Until recently, use of TT architectures has been less common outside these sectors — but this situation is now changing rapidly, as developers in many different organisations experience the benefits of a time-triggered solution.

We provide an introduction to TT architectures on this page, and make some suggestions for ways in which you can determine whether a TT approach may offer benefits for your own organisation.

What is a time-triggered embedded system?

Time-triggered architectures are appropriate for high-end consumer goods

There are two main architectures used to develop software for modern embedded systems: these can be labelled as “event triggered” and “time triggered”.

For many developers, event-triggered (or “ET”) architectures are more familiar. ET designs involve creating systems which handle multiple interrupts. For example, interrupts may arise from periodic timer overflows, the arrival of messages on a CAN bus, the pressing of a switch, the completion of an analogue-to-digital conversion and so on. To create such systems, the developer may write code to handle the various events directly: this will typically involve creating an “interrupt service routine” to deal with each event. Alternatively, the developer may employ a conventional real-time operating system (RTOS) to support the event handling. Whether an RTOS is used or not, the end result is the same: the system must be designed in such a way that events – which may occur at “random” points in time, and in various combinations – can always be handled correctly.

The alternative to an event-triggered architecture is a time-triggered (“TT”) architecture. Although TT architectures are widely used in industries such as aerospace and medical systems, they are less familiar to developers of mainstream embedded systems. When implementing TT systems, there is only one interrupt enabled. This single interrupt is usually linked to a timer “Tick”, which might occur (for example) every millisecond. This Tick drives all activity in the system.

If you come from an “ET” background, then working with “just one interrupt” may sound like a significant challenge, but (with a little experience and the correct tools) it’s far easier than you may imagine — and use of a TT architecture can have very significant benefits for organisations that need to produce reliable embedded systems.

What are the benefits of using TT architectures in embedded systems?

Time-triggered architectures are appropriate for industrial vehicles and related products

Use of TT architectures in your system may deliver some or all of the following benefits for your organisation:

  • Reduced testing time (and faster time to market)
  • Improved product reliability
  • Reduced maintenance / warranty / product recall costs
  • Immunity from “priority inversion”
  • Ease of certification
  • Reduced legal concerns
  • Reduced unit costs

We consider each of these issues in turn below.

Reduced testing time (and faster time to market)

In many cases, the first benefit that most organisations notice when they adopt a TT solution is that the time taken to test their systems is substantially reduced. This helps to ensure that organisations can get reliable products to market much more quickly.

TT systems are easy to test because we always know exactly what the system should be doing at every point in time, and we can (therefore) quickly tell if something is wrong.

If your company is still using a conventional RTOS and / or an ET system design involving large numbers of interrupts, ask yourself how many people in your team really understand how this system works, in detail? Will it ever be possible to work out exactly what will happen if (say) Interrupt 10 is triggered just after Interrupt 6, while Interrupts 2 and Interrupt 3 are being serviced? Just how many possible combinations are there to consider during testing — and will you have to repeat all of the tests again after every small change?

If your team members don’t fully understand how the system operates, how can they be sure that they have really finished testing it prior to release to customers — and how can you ever know exactly how your product will operate in the field?

Improved product reliability

The key advantage provided by TT designs is that they have extremely predictable behaviour. This, in turn, leads directly to the creation of more reliable products.

One reason that TT designs are more reliable is that we always know what state the system (both hardware and software) will be in when an interrupt occurs: this means that we can — when required — provide timing guarantees for key activities at resolutions of microseconds (or even machine cycles, where this is needed). One consequence is that control and data sampling applications can provide extremely high levels of performance (with no “jitter”).

Reduced maintenance / warranty / product recall costs

The predictable behaviour of TT systems — and the fact that you can be sure that your system has been fully tested before release — translates directly into lower warranty costs, and means that it is much less likely that you will ever need to recall products.

Where systems need to be maintained or upgraded in the field, a TT solution is — again — an excellent starting, point because the impact of changes to any part of the system can be predicted in advance.

Immunity from “priority inversion”

Priority inversion occurs in an ET system when a task of low priority can prevent a task of higher priority from running. In the worst case scenario, the result can be total deadlock (when the system “hangs” completely). Partial solutions are available, but it is impossible to deal with the problem completely in an ET design.

By contrast, TT designs are immune to priority inversion. This provides significant benefits in many applications, including improved system performance and reduce code complexity.

In any ET design in which tasks can pre-empt one another, we must guard against serious problem which arise as a result of priority inversion and deadlock. Such problems can be reduced if we implement “priority ceiling” protocols correctly — but they can never be removed completely and must be considered carefully during design reviews and when testing the system. By contrast, TT designs are immune from priority inversion (even in systems which support task pre-emption).

[Video 4 in our Certification series illustrates some of the challenges caused by priority inversion — and demonstrates why TT designs are not susceptible to this problem.]

Ease of certification

Many systems for use in aerospace, medical, automotive and other sectors require certification.

Because of the predictable nature of TT designs, certification authorities tend to look very favourably upon the use of this architecture in safety-critical and safety-related systems.

Some recent standards even make explicit recommendations about the use of TT architectures: for example, the “ISO 26262” standard (released in 2011).

Reduced legal concerns

Even where your organisation may not be subject to specific certification requirements, there is always a concern that — in the event that one of your designs is alleged to have contributed to a situation in which people were injured or killed, or which has resulted in significant financial loss — you may be required to demonstrate that you followed “best practice” when developing your product.

An appropriate use of TT architectures can be a core part of a “best practice” solution in these unfortunate circumstances.

Reduced unit costs

Last (but not least), many companies find that use of TT architectures helps to reduce costs of production, not least because it reduces system resource requirements.

There are two main reasons for this:

  • Organisations which employ a TT solution find that they can determine maximum CPU loading levels with great accuracy (much more accurately than is possible with an ET solution). As a result, TT designs can run safely at very high levels of CPU loading and can make very effective use of lower-cost processors.
  • TT designs don’t require a concentional RTOS: this further reduces resource requirements (and royalty costs).

Practical examples of TT architectures in practice

TT architectures can be used:

  • With sets of co-operative (“non-pre-emptive”) tasks
  • In systems which support task pre-emption
  • In distributed (multi-processor) systems based on Controller Area Network, RS-485, etc.

You’ll find numerous practical examples of these types of designs in the following books (written by a member of our team).

Embedded C

“Embedded C” provides an introduction to the programming of embedded systems using time-triggered software architectures.

Cover of Embedded C

  • Pont, M.J.(2002) “Embedded C”, Addison-Wesley. ISBN: 0-201-79523-X.
  • Pont, M.J.(2003) “Embedded C”, Chinese Electric Power Press. ISBN: 7-5083-1814-5.
  • Pont, M.J.(2004) “Embedded C”, Pearson Education Taiwan. ISBN: 986-7491-52-1.
  • Pont, M.J.(2008) “Embedded C”, Dorling Kindersley (India) Pvt. Ltd. ISBN: 978-81-317-1589-5.

Patterns for time-triggered embedded systems

“Patterns for Time-Triggered Embedded Systems” provides more detailed coverage of the use of time-triggered techniques in reliable embedded systems.

Please note that “PTTES” can now be downloaded without charge from this website.

Cover of Pattern for Time-Triggered Embedded Systems

  • Pont, M.J.(2001) “Patterns for Time-Triggered Embedded Systems”, Addison-Wesley / ACM Press. ISBN: 0-201-331381.
  • Pont, M.J.(2004) “Patterns for time-triggered embedded systems”, Chinese Electric Power Press ISBN: 7-5083-2206-1.

Who should use TT architectures?

Time-triggered architectures are appropriate for high-end consumer goods

Techniques for the development of reliable embedded systems are — clearly — of great concern in safety-critical markets (e.g. the aerospace industries), where system failures can have fatal consequences. TT techniques have been used for many years in such sectors.

At what might be seen as the “other end of the reliability spectrum”, embedded processors now also have an enormous impact in much broader areas of product development, including high-end consumer applications such as washing machines and set-top boxes. Manufacturers need to maximise the reliability of all such systems in order to reduce the cost of warranty repairs, minimise product recalls and ensure repeat orders — and we have found that TT architectures can be used very effectively in these sectors too.

Between the above “higher end” and “lower end” systems, there are numerous other safety-related (and sometimes safety-critical) systems. For example, recent developments in the automotive sector — both for petrol / diesel vehicles and electric vehicles — have seen a very large increase in the use of embedded processors in passenger cars and other road vehicles. The need to ensure that such systems are developed to a very high standard has been recognised by the introduction of ISO 26262 and related standards and guidelines. Many organisations are now recognising that their “traditional” ET architectures are unable to meet modern requirements and they are looking for alternative solutions.

Why doesn’t everyone already use TT architectures in embedded systems?

Time-triggered architectures are appropriate for medical systems

We’ve argued in the sections above that TT architectures have many clear benefits — it would therefore be reasonable to ask why this isn’t the “standard” way of developing embedded systems?

The explanation is not complicated:

Testing a TT system is (compared to an equivalent ET system) generally considered to be straightforward — but building the TT system in the first place is generally considered to be more challenging than creating an equivalent ET system .

When we first began working on this problem in the 1990s, the goal was clear: we needed to develop processes and products which would make it much easier for organisations to create effective TT designs.

We believe that we have achieved this goal:

Want to learn more about TT architectures?

Time-triggered architectures are appropriate for use in passenger cars developed to ISO 26262 and related standards

Attending one of our free training days is a great way to learn about the ways in which use of TT architectures may be able to help your organisation to create reliable embedded systems.

You may also wish to consider attending our training Module “A1a” and / or Module “A2a” to gain a greater understanding of TT technology. Please note that Module A1a is now also available as a DVD Training Package.

Would use of a TT architecture help your organisation to create reliable embedded systems?

We never pretend that use of a TT architecture is the right solution for every system design — but we do find that many organisations can benefit from adopting a TT approach (or a “more TT” approach).

Example demonstration system If you are interested in finding out whether use of TT architectures may offer business benefits for your organisation, we are able to offer a cost-effective and low-risk evaluation process which will take up very little of your time.

Here’s how we often work with a new customer:

  • Both parties sign a mutual non-disclosure agreement (NDA);
  • You provide us with an example of one of your products or designs;
  • If we think we can help then — for an agreed (fixed) fee and to an agreed timetable — our highly-experienced team will create a TT version of your system for you.
  • We will also create a detailed report describing our demonstration system (and comparing it with your original design). Our report will compare performance, resource requirements and reliability issues for the original system and our modified version.

At the end of the development process, we will demonstrate our solution to you on your site (with a presentation, and Q&A session involving your entire team, if you wish). You are then free to evaluate our design (at your leisure), in order to determine whether use of our products may be of benefit to your organisation.

Many of our existing customers have been introduced to the benefits of our products in this way.

You will be under no obligation to make any further purchases from us as the result of such an evaluation process (we think the results will speak for themselves).

For further information, please contact us for an initial discussion.

Is it possible to convert an ET design to TT?

Time-triggered architectures are appropriate for use in electric vehicles

It may be tempting to assume that conversion between ET and TT designs will simply involve converting all event-handling software routines into periodic activities. However, the required software changes to the software architecture are – in many cases – rather more profound.

We’ve worked with Farah Lakhani and other researchers in the Embedded Systems Research Group at the University of Leicester to produce a collection of design patterns which can assist in the migration from ET to TT architectures.

Other relevant publications

Since the 1990s, members of our team have been involved in the development of a range of techniques and tools which support the creation and verification of time-triggered embedded systems. Over this period, we have contributed to a number of publications in this field, many of which are in the public domain. A list of some relevant publications is included below.

Ahmad, N. and Pont, M.J.(2009) “Remote debugging of embedded systems which employ a time-triggered architecture”, Proceedings of the 5th UK Embedded Forum, Leicester, UK, 23-24 September, 2009, pp.97-106. Published by Newcastle University. ISBN 978-0-7017-0222-9.

Ahmad, N. and Pont, M.J.(2010) “Debugging remote embedded systems: The impact of system software architecture”, Proceedings of the 2010 UK Electronics Forum, Newcastle, UK, 30 June-1 July, 2010, pp.17-23. Published by Newcastle University. ISBN 978-0-7017-0232-8.

Amir, M. and Pont, M.J.(2008) “Synchronising tasks in wireless multi-processor environments using a shared-clock architecture: A pilot study”, Proceedings of the 4th UK Embedded Forum, Southampton, UK, 9-10 September, 2008, pp.30-39. Published by IET. ISBN 978-0-8634-1949-2.

Amir, M. and Pont, M.J.(2009) “A time-triggered communication protocol for CAN-based networks with a star topology”, Proceedings of the 5th UK Embedded Forum, Leicester, UK, 23-24 September, 2009, pp.30-44. Published by Newcastle University. ISBN 978-0-7017-0222-9.

Amir, M. and Pont, M.J.(2010) “A novel shared-clock scheduling protocol for fault-confinement in CAN-based distributed systems”, Proceedings of the 5th IEEE International Conference on System of Systems, IEEE SoSE 2010, Loughborough University, UK, 22nd-24th, June 2010.

Amir, M. and Pont, M.J.(2010) “A time-triggered communication protocol for CAN-based networks with a fault-tolerant star topology “, Proceedings of the International Symposium on Advanced Topics in Embedded Systems and Applications under the 7th IEEE International Conference on Embedded Software and Systems, Bradford, West Yorkshire, UK, 29th June-1st July, 2010. ISBN 978-0-7695-4108-2.

Amir, M. and Pont, M.J.(2010) “Integration of TTC-SC5 and TTC-SC6 shared-clock protocols”, Proceedings of the 1st UK Electronics Forum, Newcastle, UK, 30th June-1st July, 2010. Published by Newcastle University. ISBN 978-0-7017-0232-8.

Athaide, K., Hughes, Z.M. and Pont, M.J.(2007) “Towards a time-triggered processor”, Proceedings of the 3rd UK Embedded Forum, Durham, UK, 203 April, 2007, pp.166. Published by IET. ISBN 9780863418037. ISSN 0537-9989.

Athaide, K.F., Pont, M.J. and Ayavoo, D. (2008) “Deploying a time-triggered shared-clock architecture in a multiprocessor system-on-chip design”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).

Athaide, K.F., Pont, M.J. and Ayavoo, D. (2008) “Shared-clock methodology for time-triggered multi-cores”, in Susan Stepney, Fiona Polack, Alistair McEwan, Peter Welch, and Wilson Ifill (Eds.), “Communicating Process Architectures 2008”, IOS Press.

Ayavoo, D., Pont, M.J. and Parker, S. (2004) “Using simulation to support the design of distributed embedded control systems: A case study”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.54-65. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].

Ayavoo, D., Pont, M.J. and Parker, S. (2005) “Observing the development of a reliable embedded system”. In Vardanega, T and Wellings, A. (Eds.) “Proceedings of the 10th Ada-Europe International Conference on Reliable Software Technologies, York, UK, June 20-24 2005”, pp. 167-179. Lecture Notes in Computer Science, Vol. 3555. Published by Springer-Verlag [ISBN: 3-540-26286-5]

Ayavoo, D., Pont, M.J. and Parker, S. (2006) “Does a ‘simulation first’ approach reduce the effort involved in the development of distributed embedded control systems?”. Proceedings of the 6th UKACC International Control Conference, Glasgow, Scotland, 2006.

Ayavoo, D., Pont, M.J., Fang, J., Short, M. and Parker, S. (2005) “A ‘Hardware-in-the Loop’ testbed representing the operation of a cruise-control system in a passenger car”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.60-90. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Ayavoo, D., Pont, M.J., Short, M. and Parker, S. (2005) “Two novel shared-clock scheduling algorithms for use with CAN-based distributed systems”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.246-261. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Ayavoo, D., Pont, M.J., Short, M. and Parker, S. (2007) “Two novel shared-clock scheduling algorithms for use with CAN-based distributed systems”, Microprocessors and Microsystems, 31(5): 326-334.

Bautista, R., Pont, M.J. and Edwards, T. (2005) “Comparing the performance and resource requirements of ‘PID’ and ‘LQR’ algorithms when used in a practical embedded control system: A pilot study”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.262-289. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Bautista-Quintero, R. and Pont, M.J.(2006) “Is fuzzy logic a practical choice in resource-constrained embedded control systems implemented using general-purpose microcontrollers?”, Proceedings of the 9th IEEE International Workshop on Advanced Motion Control (Istanbul, March 27-29, 2006), Volume 2, pp.692-697. IEEE catalog number 06TH8850. ISBN 0-7803-9511-5.

Bautista-Quintero, R. and Pont, M.J.(2008) “Implementation of H-infinity control algorithms for sensor-constrained mechatronic systems using low-cost microcontrollers”, IEEE Transactions on Industrial Informatics, 16(4): 175-184.

Chan, K.L. and Pont, M.J.(2010) “Real-time non-invasive detection of timing-constraint violations in time-triggered embedded systems”, Proceedings of the 7th IEEE International Conference on Embedded Software and Systems, Bradford, UK, 2010, pp.1978-1986. Published by IEEE Computer Society. ISBN 978-0-7695-4108-2.

Edwards, T., Pont, M.J., Scotson, P. and Crumpler, S. (2004) “A test-bed for evaluating and comparing designs for embedded control systems”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.106-126. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].

Edwards, T., Pont, M.J., Short, M.J., Scotson, P. and Crumpler, S. (2005) “An initial comparison of synchronous and asynchronous network architectures for use in embedded control systems with duplicate processor nodes”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.290-303. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Gendy, A. and Pont, M.J.(2007) “Towards a generic ‘single-path programming’ solution with reduced power consumption”, Proceedings of the ASME 2007 International Design Engineering Technical Conferences & Computers and Information in Engineering Conference (IDETC/CIE 2007), September 4-7, 2007, Las Vegas, Nevada, USA.

Gendy, A. and Pont, M.J.(2008) “Automating the processes of selecting an appropriate scheduling algorithm and configuring the scheduler implementation for time-triggered embedded systems”, Proceedings of The 27th International Conference on Computer Safety, Reliability and Security (SAFECOMP08), 22-25 September 2008, Newcastle upon Tyne, UK

Gendy, A. and Pont, M.J.(2008) “Automating the processes of selecting an appropriate scheduling algorithm and configuring the scheduler implementation for time-triggered embedded systems”, Proceedings of The 27th International Conference on Computer Safety, Reliability and Security (SAFECOMP08), 22-25 September 2008, Newcastle upon Tyne, UK

Gendy, A., Dong, L. and Pont, M.J.(2007) “Improving the performance of time-triggered embedded systems by means of a scheduler agent”, Proceedings of the ASME 2007 International Design Engineering Technical Conferences & Computers and Information in Engineering Conference (IDETC/CIE 2007), September 4-7, 2007, Las Vegas, Nevada, USA.

Gendy, A.K. and Pont, M.J.(2008) “Automatically configuring time-triggered schedulers for use with resource-constrained, single-processor embedded systems”, IEEE Transactions on Industrial Informatics, 4(1): 37-46.

Hanif, M., Pont, M.J. and Ayavoo, D. (2008) “Implementing a simple but flexible time-triggered architecture for practical deeply-embedded applications”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).

Hughes, Z.H. and Pont, M.J.(2004) “Design and test of a task guardian for use in TTCS embedded systems”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.16-25. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].

Hughes, Z.M. and Pont, M.J.(2008) “Reducing the impact of task overruns in resource-constrained embedded systems in which a time-triggered software architecture is employed”, Transactions of the Institute of Measurement and Control, Vol. 30: pp.427-450.

Hughes, Z.M., Pont, M.J. and Ong, H.L.R.(2005) “Design and evaluation of a “time-triggered” microcontroller”. Poster presentation at DATE 2005 (PhD Forum), Munich, Germany, March 2005.

Hughes, Z.M., Pont, M.J. and Ong, H.L.R.(2005) “The PH Processor: A soft embedded core for use in university research and teaching”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.224-245. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Imran, S., Short, M. and Pont, M.J.(2008) “Hardware implementation of a shared-clock scheduling protocol for CAN: A pilot study”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).

Imran, S., Short, M. and Pont, M.J.(2008) “Hardware implementation of a shared-clock scheduling protocol for CAN: A pilot study”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).

Key, S. and Pont, M.J.(2004) “Implementing PID control systems using resource-limited embedded processors”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.76-92. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].

Key, S.A., Pont, M.J. and Edwards, S. (2004) “Implementing low-cost TTCS systems using assembly language”. In: Henney, K. and Schutz, D. (Eds) Proceedings of the Eighth European conference on Pattern Languages of Programs (EuroPLoP 8), Germany, June 2003: pp.667-690. Published by Universitätsverlag Konstanz. ISBN 3-87940-788-6.

Koelmans, A., Bystrov, A. and Pont, M.J.(2004)(Eds.) “Proceedings of the First UK Embedded Forum” (Birmingham, UK, October 2004). Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].

Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (2005)(Eds.) “Proceedings of the Second UK Embedded Forum” (Birmingham, UK, October 2005). Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Kurian, S. and Pont, M.J.(2005) “Building reliable embedded systems using Abstract Patterns, Patterns, and Pattern Implementation Examples”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.36-59. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Kurian, S. and Pont, M.J.(2005) “Mining for pattern implementation examples”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.194-201. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Kurian, S. and Pont, M.J.(2006) “Evaluating and improving pattern-based software designs for resource-constrained embedded systems”. In: C. Guedes Soares & E. Zio (Eds), “Safety and Reliability for Managing Risk: Proceedings of the 15th European Safety and Reliabilty Conference (ESREL 2006), Estoril, Portugal, 18-22 September 2006”, Vol. 2, pp.1417-1423. Published by Taylor and Francis, London. ISBN: 0-415-41620-5 (for complete 3-volume set of proceedings). ISBN: 978-0-415-42314-4 (for Volume 2).

Kurian, S. and Pont, M.J.(2007) “Maintenance and evolution of resource-constrained embedded systems created using design patterns”, Journal of Systems and Software, 80(1): 32-41.

Lakhani, F. and Pont, M.J.(2010) “Using design patterns to support migration between different system architectures”, Proceedings of 5th IEEE International Conference on Systems of Systems Engineering, June 2010, Loughborough , UK.

Lakhani, F., and Pont, M.J.(2010) “Code balancing as a philosophy for change: Helping developers to migrate from event-triggered to time-triggered architectures” Proceedings of First UK Electronics Forum, 30June- 1 July 2010, Newcastle, UK , Published by Newcastle University. ISBN: 978-0-7017-0232-8

Lakhani, F., Pont, M.J. and Das, A. (2009) “Can we support the migration from event triggered to time triggered architectures using design patterns?” Proceedings of 5th UK Embedded Forum, Leicester, UK , pp. 62-67. Published by Newcastle University. ISBN: 978-0-7017-0222-9

Lakhani, F., Pont, M.J. and Das, A. (2009) “Towards a pattern language which supports the migration of systems from an event-triggered pre-emptive to a time-triggered co-operative software architecture” Proceedings of 14th Annual European Conference on Pattern Languages of Programming”, Irsee, Germany, 8-12 July 2009. published by CEUR vol. 566 . ISSN : 1613-0073

Lakhani, F., Pont, M.J. and Das, A. (2010) “Creating embedded systems with predictable patterns of behaviour, supporting the migration between event-triggered and time-triggered software architectures” Proceedings of 15th Annual European Conference on Pattern Languages of Programming” , Irsee, Germany, 7 -11 July 2010.

Li, Y. and Pont, M.J.(2002) “On selecting pre-processing techniques for fault classification using neural networks: A pilot study”, International Journal of Knowledge-Based Intelligent Engineering Systems, 6(2): 80-87.

Li, Y., Pont, M.J. and Jones, N.B.(2002) “Improving the performance of radial basis function classifiers in condition monitoring and fault diagnosis applications where ‘unknown’ faults may occur”, Pattern Recognition Letters, 23: 569-577.

Li, Y., Pont, M.J., and Jones, N.B.(1999) “A comparison of the performance of radial basis function and multi-layer Perceptron networks in a practical condition monitoring application”, Proceedings of Condition Monitoring 1999 [Swansea, UK, April 12-15, 1999] pp.577-592.

Li, Y., Pont, M.J., Jones, N.B. and Twiddle, J.A.(2001) “Using MLP and RBF classifiers in embedded condition monitoring and fault diagnosis applications”, Transactions of the Institute of Measurement & Control, 23(3): 313-339.

Li, Y., Pont, M.J., Parikh, C.R. and Jones, N.B.(2000) “Comparing the performance of three neural classifiers for use in embedded applications”, in: John, R. and Birkenhead, R. (Eds.) Advances in Soft Computing: Soft Computing Techniques and Applications, Springer-Verlag, Heidelberg, pp.34-39, [ISBN 3-7908-1257-9]

Li, Y.H., Jones, N.B. and Pont, M.J.(1998) “Applying neural networks and fuzzy logic to fault diagnosis: a review”. in John, R.I.(1998), Editor, “Proceedings of: ‘Recent Advances in Soft Computing ‘98” [Leicester, July 1998] pp.104-119. Published by DeMontfort Expertise, Leicester, UK [ISBN 185 721 2592].

Maaita, A. and Pont, M.J.(2005) “Using ‘planned pre-emption’ to reduce levels of task jitter in a time-triggered hybrid scheduler”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.18-35. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Mearns, D.D.U., Pont, M.J. and Ayavoo, D. (2008) “Towards Ctt (a programming language for time-triggered embedded systems)”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).

Muhammad, A. and Pont, M.J.(2008) “Synchronising tasks in wireless multi-processor environments using a shared-clock architecture: A pilot study”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).

Muhammad, A. and Pont, M.J.(2011) “Comments on: Two novel shared-clock scheduling algorithms for use with CAN-based distributed systems”, Microprocessors and Microsystems, Vol. 35, pp.81-82.

Mwelwa, C. and Pont, M.J.(2003) “Two new patterns to support the development of reliable embedded systems” Paper presented at the Second Nordic Conference on Pattern Languages of Programs, (“VikingPLoP 2003”), Bergen, Norway, September 2003.

Mwelwa, C., Athaide, K., Mearns, D., Pont, M.J. and Ward, D. (2007) “Rapid software development for reliable embedded systems using a pattern-based code generation tool”. SAE Transactions: Journal of Passenger Cars (Electronic and Electrical Systems), 115(7): 795-803.

Mwelwa, C., Pont, M.J. and Ward, D. (2004) “Code generation supported by a pattern-based design methodology”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.36-55. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].

Mwelwa, C., Pont, M.J. and Ward, D. (2004) “Using patterns to support the development and maintenance of software for reliable embedded systems: A case study”, Proceedings of the IEE / ACM Postgraduate Seminar on “System-On-Chip Design, Test and Technology”, Loughborough, UK, 15 September 2004. Published by IEE. ISBN: 0 86341 460 5 (ISSN: 0537-9989), pp. 15-20.

Mwelwa, C., Pont, M.J. and Ward, D. (2005) “Developing reliable embedded systems using a pattern-based code generation tool: A case study”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.177-193. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Nahas, M. and Pont, M.J.(2005) “Using XOR operations to reduce variations in the transmission time of CAN messages: A pilot study”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.4-17. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Nahas, M., Pont, M.J. and Jain, A. (2004) “Reducing task jitter in shared-clock embedded systems using CAN”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.184-194. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].

Nahas, M., Pont, M.J. and Short, M.J.(2009) “Reducing message-length variations in resource-constrained embedded systems implemented using the Controller Area Network (CAN) protocol”, Journal of Systems Architecture Vol. 55: pp.344–354.

Nahas, M., Short, M.J. and Pont, M.J.(2005) “Exploring the impact of software bit stuffing on the behaviour of a distributed embedded control system implemented using CAN”, in Proceedings of the 10th international CAN Conference, held in Rome, 8-10 March 2005, pp. 10-1 to 10-7.

Ong, H.L.R and Pont, M.J.(2001) “Empirical comparison of software-based error detection and correction techniques for embedded systems”, Proceedings of the 9th International Symposium on Hardware / Software Codesign, April 25-27 2001, Copenhagen, Denmark. Pp.230-235. Published by ACM Press, New York. ISBN: 1-58113-364-2.

Ong, H.L.R and Pont, M.J.(2002) “The impact of instruction pointer corruption on program flow: a computational modelling study”, Microprocessors and Microsystems, 25: 409-419

Ong, H.L.R, Pont, M.J. and Peasgood, W. (2001) “A comparison of software-based techniques intended to increase the reliability of embedded applications in the presence of EMI” Microprocessors and Microsystems, 24(10): 481-491.

Ong, H.L.R., Pont, M.J., and Peasgood, W. (2000) “Hardware-software tradeoffs when designing microcontroller-based applications for high-EMI environments”, IEE Colloquium on Hardware-Software Co-Design, Savoy Place, London, 8 December, 2000. IEE Colloquium Digests #111.

Parikh C.R., M.J. Pont and N.B. Jones (2001) “Application of Dempster-Shafer theory in condition monitoring systems”, Pattern Recognition Letters, 22(6-7): 777-785.

Parikh C.R., Pont, M.J., Jones, N.B. and Schlindwein, F.S.(2003) “Improving the performance of CMFD applications using multiple classifiers and a fusion framework”, Transactions of the Institute of Measurement and Control, 25(2): 123-144.

Parikh, C., Pont, M.J., Jones, N.B., Bhatti, A.I., Li, Y.H., Spurgeon, S.K., Scotson, P. and Scaife, M. (1998) “Towards an application framework for condition monitoring and fault diagnosis”. In John, R.I.(1998), Editor, “Proceedings of: ‘Recent Advances in Soft Computing ‘98” [Leicester, July 1998] pp.128-141. Published by DeMontfort Expertise, Leicester, UK [ISBN 185 721 2592].

Parikh, C.R., Pont, M.J., Li, Y. and Jones, N.B.(1999) “Improving the performance of multi-layer Perceptrons where limited training data are available for some classes”, Proceedings IEE International Conference on Neural Networks, Edinburgh, September 1999, pp.227-232.

Parikh, C.R., Pont, M.J., Li, Y. and Jones, N.B.(1999) “Neural networks for condition monitoring and fault diagnosis: The effect of training data on classifier performance”, Proceedings of Condition Monitoring 1999 [Swansea, UK, April 1999] pp.237-244.

Parikh, C.R., Pont, M.J., Li, Y. and Jones, N.B.(2000) “Investigating the performance of MLP classifiers where limited training data are available for some classes”, in: John, R. and Birkenhead, R. (Eds.) Advances in Soft Computing: Soft Computing Techniques and Applications, Springer-Verlag, Heidelberg, pp.22-27, [ISBN 3-7908-1257-9]

Parikh, C.R., Pont, M.J., Li, Y.H., Jones, N.B. and Twiddle, J.A.(1998) “Towards a flexible application framework for data fusion using real-time design patterns,” Proceedings of 6th European Congress on Intelligent Techniques & Soft Computing (EUFIT), Aachen, Germany, September 7-10, 1998. pp.1131-1135.

Phatrapornnant, T. and Pont, M.J.(2004) “The application of dynamic voltage scaling in embedded systems employing a TTCS software architecture: A case study”, Proceedings of the IEE / ACM Postgraduate Seminar on “System-On-Chip Design, Test and Technology”, Loughborough, UK, 15 September 2004. Published by IEE. ISBN: 0 86341 460 5 (ISSN: 0537-9989), pp. 3-8.

Phatrapornnant, T. and Pont, M.J.(2004) “The application of dynamic voltage scaling in embedded systems employing a TTCS software architecture”. In: Koelmans, A., Bystrov, A. and Pont, M.J.(Eds.) Proceedings of the UK Embedded Forum 2004 (Birmingham, UK, October 2004), pp.127-143. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0180-3].

Phatrapornnant, T. and Pont, M.J.(2006) “Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling”, IEEE Transactions on Computers, 55(2): 113-124.

Pont, M.J.(1996) “Software Engineering with C++ and CASE Tools”, Addison-Wesley [964 pages]. ISBN: 0-201-87718-X.

Pont, M.J.(1998) “Control system design using real-time design patterns”, Proceedings of Control ‘98 (Swansea, UK), September 1998, pp.1078-1083.

Pont, M.J.(2000) “Can patterns increase the reliability of embedded hardware-software co-designs?”, IEE Colloquium on Hardware-Software Co-Design, Savoy Place, London, 8 December, 2000. IEE Colloquium Digests #111.

Pont, M.J.(2000) “Designing and implementing reliable embedded systems using patterns”, in, Dyson, P. and Devos, Martine (Eds.) “EuroPLoP ‘99: Proceedings of the 4th European Conference on Pattern Languages of Programming and Computing, 1999”. ISBN 3-87940-774-6, Universitätsverlag Konstanz.

Pont, M.J.(2001) “Patterns for Time-Triggered Embedded Systems: Building Reliable Applications with the 8051 Family of Microcontrollers”, Addison-Wesley / ACM Press. [1012 pages] ISBN: 0-201-331381.

Pont, M.J.(2002) “Embedded C”, Addison-Wesley. [302 pages] ISBN: 0-201-79523-X.

Pont, M.J.(2003) “An object-oriented approach to software development for embedded systems implemented using C”, Transactions of the Institute of Measurement and Control 25(3): 217-238.

Pont, M.J.(2003) “Supporting the development of time-triggered co-operatively scheduled (TTCS) embedded software using design patterns”, Informatica, 27: 81-88.

Pont, M.J.(2008) “Applying time-triggered architectures in reliable embedded systems: Challenges and solutions”, Elektrotechnik & Informationstechnik, Vol. 125(11): 401-405.

Pont, M.J. and Banner, M.P.(2004) “Designing embedded systems using patterns: A case study”, Journal of Systems and Software, 71(3): 201-213.

Pont, M.J. and Mwelwa, C. (2003) “Developing reliable embedded systems using 8051 and ARM processors: Towards a new pattern language” Paper presented at the Second Nordic Conference on Pattern Languages of Programs, (“VikingPLoP 2003”), Bergen, Norway, September 2003.

Pont, M.J. and Ong, H.L.R.(2003) “Using watchdog timers to improve the reliability of TTCS embedded systems”, in Hruby, P. and Soressen, K. E.[Eds.] Proceedings of the First Nordic Conference on Pattern Languages of Programs, September, 2002 (“VikingPloP 2002”), pp.159-200. Published by Micrsoft Business Solutions. ISBN: 87-7849-769-8.

Pont, M.J., Kureemun, R., Ong, H.L.R. and Peasgood, W. (1999) “Increasing the reliability of embedded automotive applications in the presence of EMI: A pilot study”, IEE Colloquium on Automotive EMC, Birmingham, September 28, 1999.

Pont, M.J., Kurian, S. and Bautista-Quintero, R. (2007) “Meeting real-time constraints using ‘Sandwich Delays’”. In: Zdun, U. and Hvatum, L. (Eds) Proceedings of the Eleventh European conference on Pattern Languages of Programs (EuroPLoP ‘06), Germany, July 2006: pp.67-77. Published by Universitätsverlag Konstanz. ISBN 978-3-87940-813-9.

Pont, M.J., Kurian, S., Wang, H. and Phatrapornnant, T. (2007) “Selecting an appropriate scheduler for use with time-triggered embedded systems” Paper presented at the 12th European Conference on Pattern Languages of Programs (EuroPLoP 2007).

Pont, M.J., Li, Y., Parikh, C.R. and Wong, C.P.(1999) “The design of embedded systems using software patterns”, Proceedings of Condition Monitoring 1999 [Swansea, UK, April 12-15, 1999] pp.221-236.

Pont, M.J., Norman, A.J., Mwelwa, C. and Edwards, T. (2004) “Prototyping time-triggered embedded systems using PC hardware”. In: Henney, K. and Schutz, D. (Eds) Proceedings of the Eighth European conference on Pattern Languages of Programs (EuroPLoP 8), Germany, June 2003: pp.691-716. Published by Universitätsverlag Konstanz. ISBN 3-87940-788-6.

Rizvi, S.A.I. and Pont, M.J.(2009) “Hardware support for deadlock-free resource sharing in an embedded system with a TT architecture”, Proceedings of 5th UK Embedded Forum 2009, University of Leicester, UK, 23-24 September, pp. 1-9. Published by Newcastle University. ISBN: 978-0-7017-0222-9

Short, M. and Pont, M.J.(2005) “Hardware in the loop simulation of embedded automotive control systems”, in Proceedings of the 8th IEEE International Conference on Intelligent Transportation Systems (IEEE ITSC 2005) held in Vienna, Austria, 13-16 September 2005, pp. 226-231.

Short, M. and Pont, M.J.(2006) “Predicting the impact of hardware redundancy on the performance of embedded control systems”. Proceedings of the 6th UKACC International Control Conference, Glasgow, Scotland, 30 August to 1 September, 2006.

Short, M. and Pont, M.J.(2007) “Fault-tolerant time-triggered communication using CAN”, IEEE Transactions on Industrial Informatics, 3(2): 131-142.

Short, M. and Pont, M.J.(2008) “Assessment of high-integrity embedded automotive control systems using Hardware-in-the-Loop simulation”, Journal of Systems and Software, 81(7): 1163-1183.

Short, M., Fang, J., Pont, M.J. and Rajabzadeh, A. (2007) “Assessing the impact of redundancy on the performance of a brake-by-wire system”. SAE Transactions: Journal of Passenger Cars (Electronic and Electrical Systems), 115(7): 331-338.

Short, M., Pont, M.J. and Fang, J. (2008) “Assessment of performance and dependability in embedded control systems: Methodology and case study”, Control Engineering Practice. Vol. 16, pp.1293– 1307

Short, M., Pont, M.J. and Fang, J. (2008) “Exploring the impact of task pre-emption on dependability in time-triggered embedded systems: A pilot study”, Proceedings of the 20th EUROMICRO Conference on Real-Time Systems (ECRTS 08), Prague, Czech Republic, July 2nd - 4th, 2008

Short, M., Pont, M.J. and Fang, J. (2008) “Exploring the impact of task pre-emption on dependability in time-triggered embedded systems: A pilot study”, Proceedings of the 20th EUROMICRO Conference on Real-Time Systems (ECRTS 08), Prague, Czech Republic, July 2nd - 4th, 2008

Vidler, P.J. and Pont, M.J.(2005) “Automatic conversion from ‘single processor’ to ‘multi-processor’ software architectures for embedded control systems”. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R. and Brown, A. (Eds.), Proceedings of the Second UK Embedded Forum (Birmingham, UK, October 2005), pp.209-223. Published by University of Newcastle upon Tyne [ISBN: 0-7017-0191-9].

Vidler, P.J. and Pont, M.J.(2006) “Computer assisted source-code parallelisation”. In: Gavrilova, M., Gervasi, O., Kumar, V., Tan, C.J.K., Taniar, D., Laganà, A., Mun, Y. and Choo, H. (eds.) Proceedings of the IEE International Conference on Computational Science and its Applications (Glasgow, May 8-11, 2006), Part V. Lecture Notes in Computer Science (LNCS), Vol. 3984, pp.22-31.

Vladimirova, T, Bannister, N.P., Fothergill, J.C., Fraser, G..W, Lester, M., Wright, D., Pont, M.J., Barnhart, D.J. and Emam, O. (2011) “CubeSat mission for space weather monitoring”, Proceedings of the 11th Australian Space Science Conference, September 26-29 2011.

Wang, H. and Pont, M.J.(2008) “Design and implementation of a static pre-emptive scheduler with highly predictable behaviour”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).

Wang, H. and Pont, M.J.(2008) “Design and implementation of a static pre-emptive scheduler with highly predictable behaviour”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).

Wang, H., Pont, M.J. and Kurian, S. (2007) “Patterns which help to avoid conflicts over shared resources in time-triggered embedded systems which employ a pre-emptive scheduler” Paper presented at the 12th European Conference on Pattern Languages of Programs (EuroPLoP 2007).